Cicero S. Vaucher

12 papers C 1Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2026 — conf
12.1 A 74fs-Jitter, -59dBc-Spur Fractional-N DPLL Using a Supply-Resilient Time-Amplifying Dual-Ramp DTC.
ISSCC
Rishabh Gurbaxani, Cicero S. Vaucher, Masoud Babaie
2024 — conf
Automotive Radar Interference Mitigation using Phase-Coded FMCW Waveform.
JC&S
Utku Kumbul, Nikita Petrov, Cicero S. Vaucher, Alexander Yarovoy
2023 J jnl
Smoothed Phase-Coded FMCW: Waveform Properties and Transceiver Architecture.
IEEE Trans. Aerosp. Electron. Syst.
Utku Kumbul, Nikita Petrov, Cicero S. Vaucher, Alexander Yarovoy
2011 — conf
A 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applications.
ISSCC
Juan F. Osorio, Cicero S. Vaucher, Bill Huff, Edwin van der Heijden, Anton de Graauw
2010 J jnl
A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems.
IEEE J. Solid State Circuits
Yikun Yu, Peter G. M. Baltus, Anton de Graauw, Edwin van der Heijden, Cicero S. Vaucher, Arthur H. M. van Roermund
2009 — conf
Frequency Synthesizers.
CICC
Cicero S. Vaucher, Rick Booth
2008 C conf
Phase noise in frequency divider circuits.
ISCAS
Melina Apostolidou, Peter G. M. Baltus, Cicero S. Vaucher
2004 J jnl
A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS.
IEEE J. Solid State Circuits
Remco C. H. van de Beek, Cicero S. Vaucher, Domine M. W. Leenaerts, Eric A. M. Klumperink, Bram Nauta
2003 J jnl
A 15-mW fully integrated I/Q synthesizer for Bluetooth in 0.18-μm CMOS.
IEEE J. Solid State Circuits
Domine M. W. Leenaerts, Cicero S. Vaucher, Henk Jan Bergveld, Michael Thompson, Kevin Moore
2001 — conf
Design and optimization of a low jitter clock-conversion PLL for SONET/SDH optical transmitters.
ICECS
Johan van der Tang, Cicero S. Vaucher
2000 J jnl
A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology.
IEEE J. Solid State Circuits
Cicero S. Vaucher, Igor Ferencic, Matthias Locher, Sebastian Sedvallson, Urs Voegeli, Zhenhua Wang
2000 J jnl
An adaptive PLL tuning system architecture combining high spectral purity and fast settling time.
IEEE J. Solid State Circuits
Cicero S. Vaucher