Ciaran Toal

22 papers A 3B 2C 1Misc 1Journal 2Unranked 12
YearRankTypeTitle / Venue / Authors
2012 — conf
A 1Gbps FPGA-based wireless baseband MIMO transceiver.
SoCC
Ciaran Toal, Sakir Sezer, Dwayne Burns, Pei Xiao, Vincent F. Fusco
2012 J jnl
Fully hardware based WFQ architecture for high-speed QoS packet scheduling.
Integr.
Kieran McLaughlin, Dwayne Burns, Ciaran Toal, Colm McKillen, Sakir Sezer
2010 — conf
Transmit and receive filter design for OFDM based WLAN systems.
WCSP
Pei Xiao, Ciaran Toal, Dwayne Burns, Vincent F. Fusco, Colin Cowan
2009 J jnl
Design and Implementation of a Field Programmable CRC Circuit Architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Xin Yang
2007 B conf
An FPGA Based Memory Efficient Shared Buffer Implementation.
FPL
Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic
2007 — conf
An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing.
AHS
Ciaran Toal, Dwayne Burns, Kieran McLaughlin, Sakir Sezer, Stephen O'Kane
2007 — conf
FPGA-Based Lookup Circuit for Session-Based IP Packet Classification.
AHS
Motasem Abdelghani, Sakir Sezer, Emi Garcia, Jun Mu, Ciaran Toal
2007 — conf
Programmable CRC circuit architecture.
SoCC
Ciaran Toal, Sakir Sezer, Xin Yang, Kieran McLaughlin, Dwayne Burns, Tiberiu Seceleanu
2006 — conf
A VLSI GFP Frame Delineation Circuit.
ISVLSI
Ciaran Toal, Sakir Sezer, Xin Yang
2006 — —
Exploration of high performance frame processing architectures.
Ciaran Toal
2006 A conf
Investigation into programmability for layer 2 protocol frame delineation architectures.
IPDPS
Ciaran Toal, Sakir Sezer
2005 — conf
A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA.
AICT/SAPIR/ELETE
Ciaran Toal, Sakir Sezer
2005 — conf
Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch.
SoCC
Stephen O'Kane, Sakir Sezer, Ciaran Toal
2004 A conf
A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling.
IPDPS
Sakir Sezer, Ciaran Toal, Emi Garcia, Victoria Stewart
2004 — conf
Architecture and implementation of a novel tag computation circuit for broadband wireless access packet scheduling.
ICC
Sakir Sezer, Emi Garcia-Palacios, Ciaran Toal, Stephen Dawson
2004 — conf
Exploration of GFP frame delineation architectures for network processing.
SoCC
Ciaran Toal, Sakir Sezer
2004 — conf
Implementation of a Novel Credit Based SCFQ Scheduler for Broadband Wireless Access.
ICT
Emi Garcia-Palacios, Sakir Sezer, Ciaran Toal, Stephen Dawson
2004 — conf
The Implementation of Scalable ATM Frame Delineation Circuits.
ICT
Ciaran Toal, Sakir Sezer
2003 C conf
A 32-Bit SoPC Implementation of a P5.
ISCC
Ciaran Toal, Sakir Sezer
2003 Misc conf
A Pipelined SoPC Architecture for 2.5 Gbps Network Processing.
FCCM
Ciaran Toal, Sakir Sezer, Xing Yu
2003 A conf
A Programmable and Highly Pipelined PPP Architecture for Gigabit IP over SDH/SONET.
IPDPS
Ciaran Toal, Sakir Sezer
2003 B conf
Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler.
FPL
Brendan McAllister, Sakir Sezer, Ciaran Toal