Chunhong Chen - RankMe

51 papers A 6C 8Journal 20Unranked 17

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A prospective comparison of ultrawide-field and two-field fundus imaging for diabetic retinopathy assessment. BMC Medical Imaging Yanzhen Li, Chenxi Fu, Liheng Xiu, Linyi Zhang, Xi Zhang, Chunhong Chen, Zhongwen Li
2026	J	`jnl`	Towards Integrated Sensing in Multi-Tier Multi-User MEC: A DRL-Driven RSMA-Assisted Approach. IEEE Trans. Veh. Technol. Chunhong Chen, Le He, Lisheng Fan, Xianfu Lei, Arumugam Nallanathan
2022	—	`conf`	A Hybrid Method for Signal Probability Estimation with Combinational Circuits. APCCAS Chunhong Chen, Suoyue Zhan
2022	J	`jnl`	A hybrid method for signal probability and reliability estimation with combinational circuits. Integr. Suoyue Zhan, Chunhong Chen
2022	—	`conf`	An Efficient Method for Sequential Circuit Reliability Estimation. MWSCAS Suoyue Zhan, Chunhong Chen
2022	J	`jnl`	Area-Efficient Finite Field Multiplication Using Hybrid SET-MOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Chen Zhang, Huapeng Wu, Chunhong Chen
2022	—	`conf`	Circuit Reliability Analysis with Considerations of Aging Effect. SBCCI Suoyue Zhan, Chunhong Chen
2021	—	`conf`	An Analytical Model for Circuit Reliability Estimation. MWSCAS Khawja Sikander, Suoyue Zhan, Chunhong Chen
2021	—	`conf`	Area-Efficient Finite Field Multiplication in $\text{GF} (2^{n})$ Using Single-Electron Transistors. APCCAS Chen Zhang, Chunhong Chen, Huapeng Wu
2019	—	`conf`	Allocating Gate Reliability for Circuit Reliability Optimization. MWSCAS Suoyue Zhan, Khawja Sikander, Chunhong Chen
2018	C	`conf`	A Triple-Point Model for Circuit-Level Reliability Analysis. ISCAS Chunhong Chen, Jinchen Cai, Suoyue Zhan
2018	—	`conf`	Modeling and Application for Negative-Differential-Conductance Devices with Single-Electron Technology. MWSCAS Lin Li, Chunhong Chen
2017	—	`conf`	Circuit Reliability Analysis Using Signal Reliability Correlations. QRS Companion Jinchen Cai, Chunhong Chen
2015	J	`jnl`	A fast model for analysis and improvement of gate-level circuit reliability. Integr. Chunhong Chen, Ran Xiao
2015	C	`conf`	Power optimization design for probabilistic logic circuits. ISCAS Ran Xiao, Chunhong Chen
2014	J	`jnl`	Gate-Level Circuit Reliability Analysis: A Survey. VLSI Design Ran Xiao, Chunhong Chen
2014	C	`conf`	Implementation of the conscience mechanism using single-electron transfer in competitive learning. ISCAS Ran Xiao, Chunhong Chen
2013	J	`jnl`	A SET/MOS Hybrid Multiplier Using Frequency Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Guoqing Deng, Chunhong Chen
2013	—	`conf`	An ultra-low power voltage regulator for RFID application. MWSCAS Chia-Chin Liu, Chunhong Chen
2013	J	`jnl`	Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors. IEEE Trans. Very Large Scale Integr. Syst. Guoqing Deng, Chunhong Chen
2011	J	`jnl`	Low Power Chien Search for BCH Decoder Using RT-Level Power Management. IEEE Trans. Very Large Scale Integr. Syst. Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu
2011	J	`jnl`	Power efficient multi-stage CMOS rectifier design for UHF RFID tags. Integr. Shu-Yi Wong, Chunhong Chen
2009	J	`jnl`	Parameter optimization for growth model of greenhouse crop using genetic algorithms. Appl. Soft Comput. Chunni Dai, Meng Yao, Zhujie Xie, Chunhong Chen, Jingao Liu
2009	A	`conf`	Power-management-based Chien search for low power BCH decoder. ISLPED Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu
2008	C	`conf`	An experimental study on multi-island structures for single-electron tunneling based threshold logic. ISCAS Venketeshwaran Puthucode, Chunhong Chen
2008	C	`conf`	Protocol-level performance analysis for anti-collision protocols in RFID systems. ISCAS Mohammed Berhea, Chunhong Chen, Q. M. Jonathan Wu
2007	C	`conf`	Quasi-Static Energy Recovery Logic with Single Power-Clock Supply. ISCAS Shun Li, Feng Zhou, Chunhong Chen, Hua Chen, Yipin Wu
2006	J	`jnl`	A low-power CMOS analog multiplier. IEEE Trans. Circuits Syst. II Express Briefs Chunhong Chen, Zheng Li
2006	—	`conf`	Finite State Machine Implementation with Single-Electron Tunneling Technology. ISVLSI Jialin Mi, Chunhong Chen
2006	—	`conf`	Performance Evaluation and Optimization of Full Adders with Single-Electron Technology. CCECE Yanjie Mao, Chunhong Chen
2006	—	`conf`	Power-Oriented Delay Budgeting for Combinational Circuits. ISVLSI Jialin Mi, Chunhong Chen
2006	C	`conf`	Power-oriented delay budgeting for combinational circuits. ISCAS Jialin Mi, Chunhong Chen, H. K. Kwan
2005	J	`jnl`	A Novel State Encoding Algorithm for Low Power Implementation. J. Circuits Syst. Comput. Chunhong Chen, Jiang Zhao, Majid Ahmadi
2004	A	`conf`	Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems. ISLPED Feng Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min
2004	J	`jnl`	Timing driven gate duplication. IEEE Trans. Very Large Scale Integr. Syst. Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh
2003	—	`conf`	A semi-Gray encoding algorithm for low-power state assignment. ISCAS (5) Chunhong Chen, Jiang Zhao, Majid Ahmadi
2002	A	`conf`	Activity-sensitive clock tree construction for low power. ISLPED Chunhong Chen, Changjun Kang, Majid Sarrafzadeh
2002	J	`jnl`	Budget Management with Applications. Algorithmica Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava, Majid Sarrafzadeh
2002	—	`conf`	Physical design with multiple on-chip voltages. ISPD Chunhong Chen
2002	A	`conf`	Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis. DATE Chunhong Chen, Majid Sarrafzadeh
2002	J	`jnl`	Predicting potential performance for digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
2002	—	`conf`	Probabilistic Analysis of Rectilinear Steiner Trees. ASP-DAC/VLSI Design Chunhong Chen
2002	J	`jnl`	Probability-based approach to rectilinear Steiner tree problems. IEEE Trans. Very Large Scale Integr. Syst. Chunhong Chen, Jiang Zhao, Majid Ahmadi
2001	J	`jnl`	Activity-driven clock design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh
2001	J	`jnl`	On gate level power optimization using dual-supply voltages. IEEE Trans. Very Large Scale Integr. Syst. Chunhong Chen, Ankur Srivastava, Majid Sarrafzadeh
2001	J	`jnl`	Power Optimization of Delay Constrained Circuits. VLSI Design Anshuman Nayak, Malay Haldar, Prith Banerjee, Chunhong Chen, Majid Sarrafzadeh
2001	—	`conf`	Timing driven gate duplication in technology independent phase. ASP-DAC Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh
2000	A	`conf`	Potential Slack: An Effective Metric of Combinational Circuit Performance. ICCAD Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
2000	—	`conf`	Power reduction by simultaneous voltage scaling and gate sizing. ASP-DAC Chunhong Chen, Majid Sarrafzadeh
1999	C	`conf`	An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages. ICCD Chunhong Chen, Majid Sarrafzadeh
1999	A	`conf`	Provably good algorithm for low power consumption with dual supply voltages. ICCAD Chunhong Chen, Majid Sarrafzadeh