Chunghee Kim

12 papers A 2C 2Journal 4Unranked 4
YearRankTypeTitle / Venue / Authors
2021 — conf
Dynamic Differential Flip-Flop without Explicit Output Latching Stage for High-Speed SoC.
ICECS
Min-Su Kim, Wonhyun Choi, Jong-Woo Kim, Chunghee Kim, Jae-Hyuk Oh, Bai-Sun Kong
2018 C conf
Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling.
ISCAS
Min-Su Kim, Ah-Reum Kim, Yong-geol Kim, Chunghee Kim, Dong-Yeop Kim, Jong-Woo Kim, Daeseong Lee, Hyun Lee, Jungyul Pyo, Youngmin Shin, Jae Cheol Son
2016 — conf
Single-ended D flip-flop with implicit scan mux for high performance mobile AP.
SoCC
Min-Su Kim, Chunghee Kim, Yong-geol Kim, Ah-Reum Kim, Jikyum Kim, Juhyun Kang, Daeseong Lee, Changjun Choi, Ilsuk Suh, Jungyul Pyo, Youngmin Shin, Jae Cheol Son
2015 — conf
23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor.
ISSCC
Jungyul Pyo, Youngmin Shin, Hoi-Jin Lee, Sung-il Bae, Min-Su Kim, Kwangil Kim, Ken Shin, Yohan Kwon, Heungchul Oh, Jaeyoung Lim, Dong-Wook Lee, Jongho Lee, Inpyo Hong, Kyungkuk Chae, Heon-Hee Lee, Sung-Wook Lee, Seongho Song, Chunghee Kim, Jin-Soo Park, Heesoo Kim, Sunghee Yun, Ukrae Cho, Jae Cheol Son, Sungho Park
2013 C conf
Scan-controlled pulse flip-flops for mobile application processors.
ISCAS
Min-Su Kim, Hyoungwook Lee, Jin-Soo Park, Chunghee Kim, Juhyun Kang, Ken Shin, Emil Kagramanyan, Gunok Jung, Ukrae Cho, Youngmin Shin, Jae-Cheol Son
2008 J jnl
Power and Skew Aware Point Diffusion Clock Network.
IEICE Trans. Electron.
Gunok Jung, Chunghee Kim, Kyoungkuk Chae, Gi-Ho Park, Sung-Bae Park
2000 A conf
Free MDD-Based Software Optimization Techniques for Embedded Systems.
DATE
Chunghee Kim, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
1996 J jnl
A performance-driven logic emulation system: FPGA network design and performance-driven partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chunghee Kim, Hyunchul Shin
1995 — conf
Performance-driven circuit partitioning for prototyping by using multiple FPGA chips.
ASP-DAC
Chunghee Kim, Hyunchul Shin, Young-Uk Yu
1995 J jnl
Performance-oriented technology mapping for LUT-based FPGA's.
IEEE Trans. Very Large Scale Integr. Syst.
Hyunchul Shin, Chunghee Kim
1993 A conf
A combined hierarchical placement algorithm.
ICCAD
Hyunchul Shin, Chunghee Kim, Wonjong Kim, Myoungsub Oh, Kwangjoon Rhee, Seogyun Choi, Heasoo Chung
1993 J jnl
A simple yet effective technique for partitioning.
IEEE Trans. Very Large Scale Integr. Syst.
Hyunchul Shin, Chunghee Kim