Chung-Yu Wu

158 papers B 3C 35Journal 65Unranked 54
YearRankTypeTitle / Venue / Authors
2024 J jnl
Design of CMOS Analog Front-End Local-Field Potential Chopper Amplifier With Stimulation Artifact Tolerance for Real-Time Closed-Loop Deep Brain Stimulation SoC Applications.
IEEE Trans. Biomed. Circuits Syst.
Chung-Yu Wu, Chi-Wei Huang, Yu-Wei Chen, Chin-Kai Lai, Chung-Chih Hung, Ming-Dou Ker
2024 J jnl
Stimulation-Induced Artifact Removal of the Local Field Potential Through Hardware Design: Toward the Implantable Closed-Loop Deep Brain Stimulation.
IEEE Access
Yi-Hui Wu, Hsiao-Chun Lin, Chi-Wei Huang, Chung-Yu Wu, Ming-Dou Ker
2023 J jnl
A CMOS Synchronized Sample-and-Hold Artifact Blanking Analog Front-End Local Field Potential Acquisition Unit With ±3.6-V Stimulation Artifact Tolerance and Monopolar Electrode-Tissue Impedance Measurement Circuit for Closed-Loop Deep Brain Stimulation SoCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chi-Wei Huang, Chin-Kai Lai, Chung-Chih Hung, Chung-Yu Wu, Ming-Dou Ker
2022 J jnl
Design and Ex Vivo Experimental Validations of the CMOS 256-Pixel Photovoltaic-Powered Subretinal Prosthetic Chip With Auto-Adaptive Pixels for a Wide Image Illuminance Range.
IEEE Trans. Biomed. Eng.
Chung-Yu Wu, Hsuan-Hung Liu, Po-Hung Chen, Chuan-Chin Chiao, Fang-Liang Chu, Yueh-Chun Tsai, Po-Chun Chen, Wen-Yuan Tsai, Ying-Hsuen Wu, Chi-Kuan Tseng
2022 — conf
Design of CMOS Analog Front-End Electroencephalography (EEG) Amplifier with ±1-V Common-mode and ±10-mV Differential-mode Artifact Removal.
BioCAS
Chi-Wei Huang, Jian-Jun Wang, Chung-Chih Hung, Chung-Yu Wu
2021 J jnl
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification.
IEEE J. Solid State Circuits
Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Li-Yang Tang, Yen-Fu Tu, Po-Chih Chang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
2020 J jnl
CMOS 256-Pixel/480-Pixel Photovoltaic-Powered Subretinal Prosthetic Chips With Wide Image Dynamic Range and Bi/Four-Directional Sharing Electrodes and Their Ex Vivo Experimental Validations With Mice.
IEEE Trans. Circuits Syst.
Chung-Yu Wu, Chi-Kuan Tseng, Jung-Hsing Liao, Chuan-Chin Chiao, Fang-Liang Chu, Yueh-Chun Tsai, Jun Ohta, Toshihiko Noda
2020 J jnl
CMOS High-Efficiency Wireless Battery Charging System With Global Power Control Through Backward Data Telemetry for Implantable Medical Devices.
IEEE Trans. Circuits Syst.
Chung-Yu Wu, Sung-Hao Wang, Li-Yang Tang
2020 J jnl
Improved Charge Pump Design and Ex Vivo Experimental Validation of CMOS 256-Pixel Photovoltaic-Powered Subretinal Prosthetic Chip.
IEEE Trans. Biomed. Eng.
Po-Han Kuo, Oi-Ying Wong, Chi-Kuan Tzeng, Pu-Wei Wu, Chuan-Chin Chiao, Po-Hung Chen, Po-Chun Chen, Yueh-Chun Tsai, Fang-Liang Chu, Jun Ohta, Takashi Tokuda, Toshihiko Noda, Chung-Yu Wu
2020 — conf
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition.
A-SSCC
Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
2020 — conf
Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals.
EMBC
Yi-Hui Wu, Yi-Huan Ou-Yang, Chiung-Chu Chen, Chen-Yi Lee, Chung-Yu Wu, Ming-Dou Ker
2019 — conf
A 2.36μW/Ch CMOS 8-Channel EEG Acquisition Unit with Input Protection Circuits for Applications Under Transcranial Direct Current Stimulation.
BioCAS
Chung-Yu Wu, Chi-Wei Huang, Tzung-Lin Tsai
2019 — conf
A CMOS 256-Pixel Self-Photovoltaics-Powered Subretinal Prosthetic Chip with Wide Image Dynamic Range and Shared Electrodes and Its In Vitro Experimental Results on Rd1 Mice.
MWSCAS
Chung-Yu Wu, Chi-Kuan Tzeng, Shih-Yun Huang, Fang-Liang Chu, Chuan-Chin Chiao, Yueh-Chun Tsai, Jun Ohta, Toshihiko Noda
2019 J jnl
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Chi-Wei Liu, Yi-Lun Chen, Pei-Chun Liao, Shiau-Pin Lin, Ting-Wei Wang, Ming-Jie Chung, Po-Hung Chen, Ming-Dou Ker, Chung-Yu Wu
2019 J jnl
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem.
IEEE Trans. Biomed. Eng.
Xin-Hong Qian, Yi-Chung Wu, Tzu-Yi Yang, Cheng-Hsiang Cheng, Hsing-Chien Chu, Wan-Hsueh Cheng, Ting-Yang Yen, Tzu-Han Lin, Yung-Jen Lin, Yu-Chi Lee, Jia-Heng Chang, Shih-Ting Lin, Shang-Hsuan Li, Tsung-Chen Wu, Chien-Chang Huang, Sung-Hao Wang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Tai-Shih Chi, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
2019 — conf
The Design of CMOS Electrode-Tissue Impedance Measurement Circuit Using Differential Current Switch with CMFB Bias for Implantable Neuro-Modulation SoCs.
BioCAS
Chi-Wei Huang, Chi-Heng Chung, Ruei-Syuan Syu, Chung-Yu Wu
2018 J jnl
A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System.
IEEE Trans. Biomed. Circuits Syst.
Chung-Yu Wu, Cheng-Hsiang Cheng, Zhi-Xin Chen
2018 J jnl
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control.
IEEE J. Solid State Circuits
Cheng-Hsiang Cheng, Ping-Yuan Tsai, Tzu-Yi Yang, Wan-Hsueh Cheng, Ting-Yang Yen, Zhicong Luo, Xin-Hong Qian, Zhi-Xin Chen, Tzu-Han Lin, Wei-Hong Chen, Wei-Ming Chen, Sheng-Fu Liang, Fu-Zen Shaw, Cheng-Siu Chang, Yue-Loong Hsin, Chen-Yi Lee, Ming-Dou Ker, Chung-Yu Wu
2018 — conf
A Scoping Study on the Development of an Interactive Upper-Limb Rehabilitation System Framework for Patients with Stroke.
HCI (8)
Kevin C. Tseng, Alice M. K. Wong, Chung-Yu Wu, Tian-Sheuan Chang, Yu-Cheng Pei, Jean-Lon Chen
2018 C conf
An 1.97μ, W/Ch 65nm-CMOS 8-Channel Analog Front-End Acquisition Circuit with Fast-Settling Hybrid DC Servo Loop for EEG Monitoring.
ISCAS
Pin-Wen Chen, Chi-Wei Huang, Chung-Yu Wu
2018 J jnl
Introduction to the Special Issue on the 2018 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits
Chung-Yu Wu, Patrick P. Mercier
2018 C conf
The Design of CMOS 13.56-MHz High Efficiency 1×/3× 1.99V/6.29V Active Rectifier for Implantable Neuromodulation Systems.
ISCAS
Sung-Hao Wang, Yueh-Hsuan Lee, Xin-Hong Qian, Chung-Yu Wu
2017 C conf
A 16-channel CMOS chopper-stabilized analog front-end acquisition circuits for ECoG detection.
ISCAS
Cheng-Hsiang Cheng, Zhi-Xin Chen, Chung-Yu Wu
2017 C conf
A gradient vector flow snake based multi-level morphological active contour algorithm.
IGARSS
Chao-Cheng Wu, You-Lun Wu, Chung-Yu Wu, Chinsu Lin
2017 — conf
Design considerations and clinical applications of closed-loop neural disorder control SoCs.
ASP-DAC
Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Ghu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw
2017 — conf
Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface.
ASP-DAC
Masaharu Imai, Yoshinori Takeuchi, Jun Ohta, Gregg Jørgen Suaning, Chung-Yu Wu, Napoleon Torres-Martinez
2016 C conf
The design of 8-channel CMOS area-efficient low-power current-mode analog front-end amplifier for EEG signal recording.
ISCAS
Ya-Syuan Sung, Wei-Ming Chen, Chung-Yu Wu
2015 — conf
A microfabricated coil for implantable applications of magnetic spinal cord stimulation.
EMBC
Yu-Min Fu, Che-Yu Chen, Xin-Hong Qian, Yu-Ting Cheng, Chung-Yu Wu, Jui-Sheng Sun, Chien-Chun Huang, Chao-Kai Hu
2015 — conf
An 8-channel chopper-stabilized analog front-end amplifier for EEG acquisition in 65-nm CMOS.
A-SSCC
Chung-Yu Wu, Chia-Shiung Ho
2015 C conf
An 8-channel power-efficient time-constant-enhanced analog front-end amplifier for neural signal acquisition.
ISCAS
Jung-Chen Chung, Wei-Ming Chen, Chung-Yu Wu
2015 J jnl
Novel Active Comb-Shaped Dry Electrode for EEG Measurement in Hairy Site.
IEEE Trans. Biomed. Eng.
Yan-Jun Huang, Chung-Yu Wu, Alice May-Kuen Wong, Bor-Shyh Lin
2015 — conf
The design of CMOS self-powered 256-pixel implantable chip with on-chip photovoltaic cells and active pixel sensors for subretinal prostheses.
BioCAS
Chung-Yu Wu, Wei-Jie Sung, Po-Han Kuo, Chi-Kuan Tzeng, Chuan-Chin Chiao, Yueh-Chun Tsai
2014 J jnl
A 13.56 MHz 40 mW CMOS High-Efficiency Inductive Link Power Supply Utilizing On-Chip Delay-Compensated Voltage Doubler Rectifier and Multiple LDOs for Implantable Medical Devices.
IEEE J. Solid State Circuits
Chung-Yu Wu, Xin-Hong Qian, Ming-Seng Cheng, Yu-An Liang, Wei-Ming Chen
2014 — conf
A 65nm CMOS low-power MedRadio-band integer-N cascaded phase-locked loop for implantable medical systems.
EMBC
Yi-Xiao Wang, Wei-Ming Chen, Chung-Yu Wu
2014 J jnl
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control.
IEEE J. Solid State Circuits
Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Yue-Loong Hsin, Sheng-Fu Liang, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Chung-Yu Wu
2013 — conf
A CMOS MedRadio-band low-power integer-N cascaded phase-locked loop for implantable medical SOCs.
BioCAS
Yu-Yu Liao, Wei-Ming Chen, Chung-Yu Wu
2013 J jnl
A CMOS Power-Efficient Low-Noise Current-Mode Front-End Amplifier for Neural Signal Recording.
IEEE Trans. Biomed. Circuits Syst.
Chung-Yu Wu, Wei-Ming Chen, Liang-Ting Kuo
2013 C conf
A Low power 10bit 500kS/s delta-modulated SAR ADC (DMSAR ADC) for implantable medical devices.
ISCAS
Yuan-Fu Lyu, Chung-Yu Wu, Li-Chen Liu, Wei-Ming Chen
2013 — conf
A MedRadio-band low-energy-per-bit 4-Mbps CMOS OOK receiver for implantable medical devices.
EMBC
Chia-Wei Chou, Li-Chen Liu, Chung-Yu Wu
2013 — conf
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control.
ISSCC
Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Shun-Ting Chang, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Sheng-Fu Liang, Tzu-Chieh Chien, Sih-Yen Wu, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Jin-Chern Chiou, Chih-Wei Chang, Lei-Chun Chou, Chung-Yu Wu
2013 J jnl
Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tai-You Lu, Chi-Yao Yu, Wei-Zen Chen, Chung-Yu Wu
2012 C conf
A low-power current-mode front-end acquisition system for biopotential signal recording.
ISCAS
Wei-Ming Chen, Liang-Ting Kuo, Chung-Yu Wu
2012 — conf
Live demonstration: The implementation of CMOS biopotential signal recording systems.
BioCAS
Wei-Ming Chen, Chung-Yu Wu
2011 J jnl
The Design of a
IEICE Trans. Electron.
Zue-Der Huang, Chung-Yu Wu
2011 — conf
The design of CMOS general-purpose analog front-end circuit with tunable gain and bandwidth for biopotential signal recording systems.
EMBC
Wei-Ming Chen, Wen-Chia Yang, Tzung-Yun Tsai, Herming Chiueh, Chung-Yu Wu
2010 C conf
45-nm Planar bulk-CMOS 23-GHz LNAs with high-Q above-IC inductors.
ISCAS
Wen-Chieh Wang, Zue-Der Huang, Geert Carchon, Abdelkarim Mercha, Stefaan Decoutere, Walter De Raedt, Chung-Yu Wu
2010 J jnl
An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications.
IEICE Trans. Electron.
Po-Hung Chen, Min-Chiao Chen, Chun-Lin Ko, Chung-Yu Wu
2010 J jnl
Design and Analysis of a CMOS Ratio-Memory Cellular Nonlinear Network (RMCNN) Requiring No Elapsed Time.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chung-Yu Wu, Sheng-Hao Chen, Yu Wu
2010 J jnl
Stability Analysis of Autonomous Ratio-Memory Cellular Nonlinear Networks for Pattern Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Su-Yung Tsai, Chi-Hsu Wang, Chung-Yu Wu
2009 J jnl
A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network.
Integr.
Fadi Riad Shahroury, Chung-Yu Wu
2009 C conf
A High Performance Linear Current Mode Image Sensor.
ISCAS
Chih-Cheng Hsieh, Wei-Yu Chen, Chung-Yu Wu
2009 J jnl
A Low-Power
IEICE Trans. Electron.
Wen-Chieh Wang, Chung-Yu Wu
2009 J jnl
The Design and Analysis of a CMOS Low-Power Large-Neighborhood CNN With Propagating Connections.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chung-Yu Wu, Sheng-Hao Chen
2008 C conf
The design of integrated 3-GHz to 11-GHz CMOS transmitter for full-band ultra-wideband (UWB) applications.
ISCAS
Wen-Chieh Wang, Chang-Ping Liao, Yi-Kai Lo, Zue-Der Huang, Fadi Riad Shahroury, Chung-Yu Wu
2007 C conf
A 24-GHz CMOS Current-Mode Power Amplifier with High PAE and Output Power.
ISCAS
Chung-Yu Wu, Shun-Wei Hsu, Wen-Chieh Wang
2007 C conf
A CMOS Expansion/Contraction Motion Sensor with a Retinal Processing Circuit for Z-motion Detection Applications.
ISCAS
Chung-Yu Wu, Chien-Ta Huang
2007 — conf
A Low Power V-band Low Noise Amplifier Using 0.13-μm CMOS Technology.
ICECS
Chung-Yu Wu, Po-Hung Chen
2007 — conf
An Integrated 60-GHz Front-end Receiver with a Frequency Tripler Using 0.13-μm CMOS Technology.
ICECS
Po-Hung Chen, Min-Chiao Chen, Chung-Yu Wu
2007 — conf
An efficient Compensation Method for Improving Luminance Uniformity of Organic Light Emitting Diode Panels.
CSC
Ming-Jong Tsai, Chao-Hsiang Feng, Chung-Yu Wu, Chang-Jung Juan
2006 — conf
A 3.110.6 GHz CMOS Direct-Conversion Receiver for UWB Applications.
ICECS
Chung-Yu Wu, Yi-Kai Lo, Min-Chiao Chen
2006 — conf
A Low-Voltage CMOS LNA Design Utilizing the Technique of Capacitive Feedback Matching Network.
ICECS
Chung-Yu Wu, Fadi Riad Shahroury
2005 — conf
A 0.8 V 5.9 GHz wide tuning range CMOS VCO using inversion-mode bandswitching varactors.
ISCAS (5)
Chung-Yu Wu, Chi-Yao Yu
2005 — conf
A Novel low power high dynamic range all CMOS Current-mode AGC.
ICECS
Chung-Yu Wu, Ismail I. Nabhan
2005 J jnl
The design of wideband and low-power CMOS active polyphase filter and its application in RF double-quadrature receivers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chung-Yun Chou, Chung-Yu Wu
2004 J jnl
A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator.
IEEE J. Solid State Circuits
Chung-Yu Wu, Chung-Yun Chou
2004 — conf
A CMOS focal-plane retinal sensor designed for shear motion detection.
ICECS
Chung-Yu Wu, Wen-Chin Hsieh, Cheng-Ta Chiang
2004 — conf
A learnable self-feedback ratio-memory cellular nonlinear network (SRMCNN) for associative memory applications.
ICECS
Jui-Lin Lai, Chung-Yu Wu
2004 — conf
A low power design on diffusive interconnection large-neighborhood cellular nonlinear network for giga-scale system application.
ICECS
Sheng-Hao Chen, Chung-Yu Wu
2004 — conf
A low-power implantable Pseudo-BJT-based silicon retina with solar cells for artificial retinal prostheses.
ISCAS (4)
Chung-Yu Wu, Felice Cheng, Cheng-Ta Chiang, Po-Kang Lin
2004 J jnl
A new CMOS pixel structure for low-dark-current and large-array-size still imager applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yu-Chuan Shih, Chung-Yu Wu
2004 J jnl
New current-mode wave-pipelined architectures for high-speed analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chung-Yu Wu, Yu-Yee Liow
2004 — conf
Optimal structure of interconnection lines for GHz giga-scale nano-CMOS system-on-chip design.
ICECS
Chung-Yu Wu, Jen-Chieh Wang
2003 — conf
A CMOS focal-plane rotation sensor with retinal processing circuit.
ESSCIRC
Kuan-Hsun Huang, Li-Ju Lin, Chung-Yu Wu
2003 B conf
A new structure of large-neighborhood cellular nonlinear network (LN-CNN).
IJCNN
Chiu-Hung Cheng, Sheng-Hao Chen, Li-Ju Lin, Kuan-Hsun Huang, Chung-Yu Wu
2003 — conf
An optimized CMOS pseudo-active-pixel-sensor structure for low-dark-current imager applications.
ISCAS (1)
Yu-Chuan Shih, Chung-Yu Wu
2003 B conf
The design of a bionic sensory chip based on the CNN model derived from the Mammalian retina.
IJCNN
Wen-Chia Yang, Li-Ju Lin, Chung-Yu Wu
2002 — conf
A new high-performance CMOS GHz power amplifier design with common-mode signal cancellation technique.
APCCAS (2)
Chung-Yu Wu, Wen-Chieh Wang, Tzung-Ming Chen
2002 — conf
An improved low-power CMOS direct-conversion transmitter for GHz wireless communication applications.
APCCAS (1)
Hong-Sing Kao, Chung-Yu Wu
2002 — conf
Improvement of pattern learning and recognition capability in ratio-memory cellular neural networks with non-discrete-type Hebbian learning algorithm.
ISCAS (1)
Chung-Yu Wu, Jui-Lin Lai
2002 — conf
The design of a new wideband and low-power CMOS active polyphase filter for low-IF receiver applications.
APCCAS (1)
Chung-Yun Chou, Chung-Yu Wu
2002 — conf
The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniques.
ISCAS (3)
Yu-Yee Liow, Chung-Yu Wu
2001 — conf
A new light-activated CMOS retinal-pulse generation circuit without external power supply for artificial retinal prostheses.
ICECS
Chung-Yu Wu, Li-Ju Lin, Kuan-Hsun Huang
2001 J jnl
On-chip ESD protection design by using polysilicon diodes in CMOS process.
IEEE J. Solid State Circuits
Ming-Dou Ker, Tung-Yang Chen, Tai-Ho Wang, Chung-Yu Wu
2001 — conf
The design of CMOS real-time motion-direction detection chip with BJT-based silicon-retina sensors and correlation-based motion detection algorithm.
ICECS
Chung-Yu Wu, Kuan-Hsun Huang, Li-Ju Lin
2001 — conf
The design of a CMOS IF bandpass amplifier with low sensitivity to process and temperature variations.
ISCAS (1)
Chung-Yu Wu, Chung-Yun Chou
2000 C conf
A compact CMOS 2 V low-power direct-conversion quadrature modulator merged with quadrature voltage-controlled oscillator and RF amplifier for 1.9 GHz RF transmitter applications.
ISCAS
Hong-Sing Kao, Chung-Yu Wu
2000 C conf
A new CMOS readout circuit for uncooled bolometric infrared focal plane arrays.
ISCAS
Tsung-Hsin Yu, Chung-Yu Wu, Pei-Yen Chen, Fa-Wen Chi, Jiunn-Jye Luo, Cheng Der Chiang, Ya-Tung Cherng
2000 C conf
Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications.
ISCAS
Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Wu, Hun-Hsien Chang
2000 J jnl
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications.
IEEE J. Solid State Circuits
Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Wu, Hun-Hsien Chang
2000 — conf
High-speed CMOS current-mode wave-pipelined analog-to-digital converter.
ICECS
Chung-Yu Wu, Yu-Yee Liow
2000 C conf
The new CMOS 2 V low-power IF fully differential Rm-C bandpass amplifier for RF wireless receivers.
ISCAS
Chung-Yu Wu, Yu Cheng, Jeng Gong
1999 — conf
A 3 V 1.9 GHz CMOS low-distortion direct-conversion quadrature modulator with a RF amplifier.
ICECS
Chung-Yu Wu, Hong-Sing Kao
1999 — conf
A new compact neuron-bipolar cellular neural network structure with adjustable neighborhood layers and high integration level.
ISCAS (6)
Wen-Cheng Yen, Chung-Yu Wu
1999 — conf
A new compact programmable νBJT cellular neural network structure with adjustable neighborhood layers for image processing.
ICECS
Wen-Cheng Yen, Chung-Yu Wu
1999 — conf
A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMs.
ISCAS (1)
Chung-Yu Wu, Yu-Yee Liow
1999 J jnl
A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications.
IEEE J. Solid State Circuits
Yuh-Kuang Tseng, Chung-Yu Wu
1999 J jnl
An improved BJT-based silicon retina with tunable image smoothing capability.
IEEE Trans. Very Large Scale Integr. Syst.
Chung-Yu Wu, Hsin-Chin Jiang
1999 — ch.
Embedded Memory.
The VLSI Handbook
Chung-Yu Wu
1999 — conf
New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's.
CICC
Ming-Dou Ker, Wen-Yu Lo, Chung-Yu Wu
1999 — conf
The design of 2 V 2.4 GHz CMOS low-noise low-power bandpass amplifier with parallel spiral inductors.
ICECS
Chung-Yu Wu, Zhong-Yun Zhou
1999 B conf
The design of CMOS cellular neural network (CNN) using the neuron-bipolar junction transistor (νBJT).
IJCNN
Chiou-Ling Yeh, Chung-Yu Wu
1999 — conf
The design of high-performance 128×128 CMOS image sensors using new current-readout techniques.
ISCAS (5)
Yu-Chuan Shih, Chung-Yu Wu
1998 J jnl
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications.
IEEE J. Solid State Circuits
Yuh-Kuang Tseng, Chung-Yu Wu
1998 J jnl
A parallel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHz RF downconversion mixer.
IEEE J. Solid State Circuits
Shuo-Yuan Hsiao, Chung-Yu Wu
1998 — conf
CMOS on-chip ESD protection design with substrate-triggering technique.
ICECS
Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Wu
1998 J jnl
High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA.
IEEE J. Solid State Circuits
Chih-Cheng Hsieh, Chung-Yu Wu, Tai-Ping Sun, Far-Wen Jih, Ya-Tung Cherng
1998 — conf
The design of 2 V 1 GHz CMOS low-noise bandpass amplifier with good temperature stability and low power dissipation.
ICECS
Chung-Yu Wu, Jeng Gong, Yu Cheng
1998 — conf
The neuron-bipolar junction transistor (v-BJT)-a new device structure for VLSI neural network implementation.
ICECS
Chung-Yu Wu, Wen-Cheng Yen
1997 J jnl
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs.
IEEE J. Solid State Circuits
Ming-Dou Ker, Hun-Hsien Chang, Chung-Yu Wu
1997 J jnl
A new cryogenic CMOS readout structure for infrared focal plane array.
IEEE J. Solid State Circuits
Chih-Cheng Hsieh, Chung-Yu Wu, Tai-Ping Sun
1997 J jnl
Focal-plane-arrays and CMOS readout techniques of infrared imaging systems.
IEEE Trans. Circuits Syst. Video Technol.
Chih-Cheng Hsieh, Chung-Yu Wu, Far-Wen Jih, Tai-Ping Sun
1997 J jnl
Guest Editorial.
IEEE Trans. Circuits Syst. Video Technol.
Bing J. Sheu, Mohammed Ghanbari, Horng-Dar Lin, Chung-Yu Wu
1997 J jnl
The design of a 3-V 900-MHz CMOS bandpass amplifier.
IEEE J. Solid State Circuits
Chung-Yu Wu, Shuo-Yuan Hsiao
1997 J jnl
The design of rotation-invariant pattern recognition using the silicon retina.
IEEE J. Solid State Circuits
Chin-Fong Chiu, Chung-Yu Wu
1996 J jnl
A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter.
IEEE J. Solid State Circuits
Shu-Yuan Chin, Chung-Yu Wu
1996 — conf
A new design technique of CMOS continuous-time VHF current-mode bandpass ladder filters using VHF bandpass biquads.
ICECS
Chung-Yu Wu, Heng-Shou Hsu
1996 J jnl
Analog electronic cochlea design using multiplexing switched-capacitor circuits.
IEEE Trans. Neural Networks
Jenn-Chyou Bor, Chung-Yu Wu
1996 — conf
Bipolar bootstrapped multi-emitter BiCMOS (B
ICECS
Chung-Yu Wu, Yuh-Kuang Tseng
1996 J jnl
CMOS current-mode neural associative memory design with on-chip learning.
IEEE Trans. Neural Networks
Chung-Yu Wu, Jeng-Feng Lan
1996 J jnl
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC.
IEEE Trans. Very Large Scale Integr. Syst.
Ming-Dou Ker, Chung-Yu Wu, Tao Cheng, Hun-Hsien Chang
1996 J jnl
Design techniques for VHF/UHF high-Q tunable bandpass filters using simple CMOS inverter-based transresistance amplifiers.
IEEE J. Solid State Circuits
Ping-Hsing Lu, Chung-Yu Wu, Ming-Kai Tsai
1996 J jnl
The design of CMOS continuous-time VHF current and voltage-mode lowpass filters with Q-enhancement circuits.
IEEE J. Solid State Circuits
Chung-Yu Wu, Heng-Shou Hsu
1995 C conf
A 1.5 V CMOS Current-Mode Cyclic Analog-to-Digital Converter with Digital Error Correction.
ISCAS
Chih-Cheng Chen, Chung-Yu Wu, Jyh-Jer Cho
1995 C conf
A 1.5V CMOS Balanced Differential Switched-Capacitor Filter with Internal Clock Boosters.
ISCAS
Chung-Yu Wu, Wei-Shinn Wey, Tsai-Chung Yu
1995 C conf
A 3-V 1-GHz Low-Noise Bandpass Amplifier.
ISCAS
Chung-Yu Wu, Shuo-Yuan Hsiao, Ron-Yi Liu
1995 J jnl
A CMOS transistor-only 8-b 4.5-Ms/s pipelined analog-to-digital converter using fully-differential current-mode circuit techniques.
IEEE J. Solid State Circuits
Chung-Yu Wu, Chih-Cheng Chen, Jyh-Jer Cho
1995 C conf
A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications.
ISCAS
Chung-Yu Wu, Jr-Houng Lu, Kuo-Hsing Cheng
1995 J jnl
A low glitch 10-bit 75-MHz CMOS video D/A converter.
IEEE J. Solid State Circuits
Tien-Yu Wu, Ching-Tsing Jih, Jueh-Chi Chen, Chung-Yu Wu
1995 J jnl
A new structure of the 2-D silicon retina.
IEEE J. Solid State Circuits
Chung-Yu Wu, Chin-Fong Chiu
1995 — conf
Analog CMOS current-mode implementation of the feedforward neural network with on-chip learning and storage.
ICNN
Jeng-Feng Lan, Chung-Yu Wu
1995 C conf
CMOS Current-Mode Outstar Neural Networks with Long-Period Analog Ratio Memory.
ISCAS
Jeng-Feng Lan, Chung-Yu Wu
1995 J jnl
CMOS current-mode implementation of spatiotemporal probabilistic neural networks for speech recognition.
J. VLSI Signal Process.
Chung-Yu Wu, Ron-Yi Liu
1995 C conf
Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's.
ISCAS
Ming-Dou Ker, Chung-Yu Wu, Hun-Hsien Chang, Tao Cheng, Tain-Shun Wu
1995 C conf
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.
ISCAS
Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu
1995 J jnl
Precise CMOS current sample/hold circuits using differential clock feedthrough attenuation techniques.
IEEE J. Solid State Circuits
Chung-Yu Wu, Chih-Cheng Chen, Jyh-Jer Cho
1995 C conf
The Design of New Low-Voltage CMOS VHF Continuous-Time Lowpass Biquaud Filters.
ISCAS
Chung-Yu Wu, Heng-Shou Hsu
1994 J jnl
A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources.
IEEE J. Solid State Circuits
Shu-Yuan Chin, Chung-Yu Wu
1994 C conf
An Alorithmic Analog-to-Digital Converter with low Ratio-and Gain-Sensitivities and 4N-Clock Conversion Cycle.
ISCAS
Shu-Yuan Chin, Chung-Yu Wu
1994 J jnl
Design techniques for tunable transresistance-C VHF bandpass filters.
IEEE J. Solid State Circuits
Ping-Hsing Lu, Chung-Yu Wu, Ming-Kai Tsai
1994 C conf
Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit.
ISCAS
Yuh-Kuang Tseng, Kuo-Hsing Cheng, Chung-Yu Wu
1994 C conf
New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems.
ISCAS
Hong-Yi Huang, Chung-Yu Wu
1994 C conf
The Continuous-Time VHF Lowpass Filter Design Using Finite-Gain Current and Voltage Amplifiers and Special Q-Enhancement Circuit.
ISCAS
Chung-Yu Wu, Heng-Shou Hsu
1994 C conf
The Design of the CMOS Current-Mode General-Purpose Analog Processor.
ISCAS
Liang-Hung Lu, Chung-Yu Wu
1994 C conf
VHF/UHF High-Q Bandpass Tunable Filters Design Using CMOS Inverter-Based Transresistnace Amplifiers.
ISCAS
Ping-Hsing Lu, Chung-Yu Wu, Ming-Kai Tsai
1993 C conf
A Ratio-independent and Gain-insensitive Algorithmic Analog-to-digital Converter.
ISCAS
Shu-Yuan Chin, Chung-Yu Wu
1993 J jnl
Analysis and design of a new race-free four-phase CMOS logic.
IEEE J. Solid State Circuits
Chung-Yu Wu, Kuo-Hsing Cheng, Jinn-Shyan Wang
1993 C conf
Chopper-stabilized Sigma-delta Modulator.
ISCAS
Ying-Hwi Chang, Chung-Yu Wu, Tsai-Chung Yu
1993 J jnl
Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic.
IEEE J. Solid State Circuits
Chung-Yu Wu, Hong-Yi Huang
1993 C conf
Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications.
ISCAS
Hong-Yi Huang, Chung-Yu Wu
1993 C conf
VHF Bandpass Filter Design Using CMOS Transresistance Amplifiers.
ISCAS
Ping-Hsing Lu, Chung-Yu Wu, Ming-Kai Tsai
1992 J jnl
A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI.
IEEE J. Solid State Circuits
Chung-Yu Wu, Ming-Dou Ker, Chung-Yuan Lee, Joe Ko
1991 J jnl
Design techniques for high-frequency CMOS switched-capacitor filters using non-op-amp-based unity-gain amplifiers.
IEEE J. Solid State Circuits
Chung-Yu Wu, Ping-Hsing Lu, Ming-Kai Tsai
1991 J jnl
Latched CMOS differential logic (LCDL) for complex high-speed VLSI.
IEEE J. Solid State Circuits
Chung-Yu Wu, Kuo-Hsing Cheng
1990 J jnl
Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters.
IEEE J. Solid State Circuits
Chung-Yu Wu, Ming-Chuen Shiau
1990 J jnl
Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Yu Wu, Ming-Chuen Shiau
1989 J jnl
CMOS nonthreshold logic (NTL) and cascode nonthreshold logic (CNTL) for high-speed applications.
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Chung-Yu Wu, Ming-Kai Tsai
1989 J jnl
New monolithic switched-capacitor differentiators with good noise rejection.
IEEE J. Solid State Circuits
Chung-Yu Wu, Tsai-Chung Yu, Shin-Shi Chang
1985 J jnl
An Efficient Timing Model for CMOS Combinational Logic Gates.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Yu Wu, Jen-Sheng Hwang, Chin Chang, Ching-Chu Chang