Chung-Yang Huang

29 papers A* 3A 11Journal 5Unranked 10

Year	Rank	Type	Title / Venue / Authors
2017	A*	`conf`	Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation. CVPR Kuan-Lun Tseng, Yen-Liang Lin, Winston H. Hsu, Chung-Yang Huang
2017	J	`jnl`	Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation. CoRR Kuan-Lun Tseng, Yen-Liang Lin, Winston H. Hsu, Chung-Yang Huang
2013	J	`jnl`	Match and Replace: A Functional ECO Engine for Multierror Circuit Rectification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shao-Lun Huang, Wei-Hsun Lin, Po-Kai Huang, Chung-Yang Huang
2012	—	`conf`	A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints. ASP-DAC Shihheng Tsai, Man-Yu Li, Chung-Yang Huang
2012	A	`conf`	Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction. DATE Kai-Fu Tang, Po-Kai Huang, Chun-Nan Chou, Chung-Yang Huang
2011	—	`conf`	A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization. ASP-DAC Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang Huang
2011	A	`conf`	Property-specific sequential invariant extraction for SAT-based unbounded model checking. ICCAD Hu-Hsi Yeh, Cheng-Yin Wu, Chung-Yang Huang
2011	—	`conf`	SoC HW/SW verification and validation. ASP-DAC Chung-Yang Huang, Yu-Fan Yin, Chih-Jen Hsu, Thomas B. Huang, Ting-Mao Chang
2011	A	`conf`	Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. DATE Yu-Fu Yeh, Chung-Yang Huang, Chi-An Wu, Hsin-Cheng Lin
2011	A	`conf`	Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques. ICCAD Bo-Han Wu, Chun-Ju Yang, Chia-Cheng Tso, Chung-Yang Huang
2010	A	`conf`	A robust functional ECO engine by SAT proof minimization and interpolation techniques. ICCAD Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, Jie-Hong Roland Jiang
2010	—	`conf`	A unified multi-corner multi-mode static timing analysis engine. ASP-DAC Jing-Jia Nian, Shihgeng Tsai, Chung-Yang Huang
2010	—	`conf`	Automatic constraint generation for guided random simulation. ASP-DAC Hu-Hsi Yeh, Chung-Yang Huang
2010	A	`conf`	Formal deadlock checking on high-level SystemC designs. ICCAD Chun-Nan Chou, Chang-Hong Hsu, Yueh-Tung Chao, Chung-Yang Huang
2010	—	`conf`	Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling. ASP-DAC Kuen-Huei Lin, Siao-Jie Cai, Chung-Yang Huang
2010	J	`jnl`	To SAT or Not to SAT: Scalable Exploration of Functional Dependency. IEEE Trans. Computers Jie-Hong Roland Jiang, Chih-Chun Lee, Alan Mishchenko, Chung-Yang Huang
2009	A*	`conf`	A false-path aware formal static timing analyzer considering simultaneous input transitions. DAC Shihheng Tsai, Chung-Yang Huang
2009	A	`conf`	Interpolant generation without constructing resolution graph. ICCAD Chih-Jen Hsu, Shao-Lun Huang, Chi-An Wu, Chung-Yang Huang
2009	—	`conf`	SAT-controlled redundancy addition and removal: a novel circuit restructuring technique. ASP-DAC Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung-Yang Huang
2008	A	`conf`	Improving Constant-Coefficient Multiplier Verification by Partial Product Identification. DATE Chao-Yue Lai, Chung-Yang Huang, Kei-Yong Khoo
2007	—	`conf`	QuteIP: An IP qualification framework for System on Chip. SoCC Hsing-Chih Hung, Ting-Hao Lin, Chung-Yang Huang
2007	A	`conf`	QuteSAT: a robust circuit-based SAT solver for complex circuit structure. DATE Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang Huang
2007	A	`conf`	Scalable exploration of functional dependency by interpolation and incremental SAT solving. ICCAD Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko
2001	—	`conf`	An analysis of ATPG and SAT algorithms for formal verification. HLDVT Ganapathy Parthasarathy, Chung-Yang Huang, Kwang-Ting Cheng
2001	J	`jnl`	Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Yang Huang, Kwang-Ting Cheng
2000	J	`jnl`	AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer
2000	A*	`conf`	Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. DAC Chung-Yang Huang, Kwang-Ting Cheng
2000	A	`conf`	Static property checking using ATPG vs. BDD techniques. ITC Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng
1998	—	`conf`	LIBRA - a library-independent framework for post-layout performance optimization. ISPD Chung-Yang Huang, Yucheng Wang, Kwang-Ting Cheng