| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2017 | A* | conf |
CVPR
|
| 2017 | J | jnl |
CoRR
|
| 2013 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2012 | — | conf |
ASP-DAC
|
| 2012 | A | conf |
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction.
DATE
|
| 2011 | — | conf |
ASP-DAC
|
| 2011 | A | conf |
ICCAD
|
| 2011 | — | conf |
ASP-DAC
|
| 2011 | A | conf |
DATE
|
| 2011 | A | conf |
ICCAD
|
| 2010 | A | conf |
ICCAD
|
| 2010 | — | conf |
ASP-DAC
|
| 2010 | — | conf |
ASP-DAC
|
| 2010 | A | conf |
ICCAD
|
| 2010 | — | conf |
Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling.
ASP-DAC
|
| 2010 | J | jnl |
IEEE Trans. Computers
|
| 2009 | A* | conf |
DAC
|
| 2009 | A | conf |
ICCAD
|
| 2009 | — | conf |
ASP-DAC
|
| 2008 | A | conf |
DATE
|
| 2007 | — | conf |
SoCC
|
| 2007 | A | conf |
DATE
|
| 2007 | A | conf |
ICCAD
|
| 2001 | — | conf |
HLDVT
|
| 2001 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2000 | J | jnl |
IEEE Trans. Computers
|
| 2000 | A* | conf |
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques.
DAC
|
| 2000 | A | conf |
ITC
|
| 1998 | — | conf |
ISPD
|