Chung-Len Lee - RankMe

56 papers A 5Misc 2Journal 23Unranked 26

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	A snake addressing scheme for phase change memory testing. Sci. China Inf. Sci. Xiaole Cui, Zuolin Cheng, Chung-Len Lee, Xinnan Lin, Yiqun Wei, Xiaogang Chen, Zhitang Song
2009	J	`jnl`	A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. IEEE Trans. Very Large Scale Integr. Syst. Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2007	J	`jnl`	A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. IEEE Trans. Very Large Scale Integr. Syst. Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu
2007	J	`jnl`	IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electron. Test. Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2007	J	`jnl`	Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2006	A	`conf`	A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. ITC Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu
2006	J	`jnl`	IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen
2006	—	`conf`	IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen
2005	—	`conf`	A Scan Matrix Design for Low Power Scan-Based Test. Asian Test Symposium Shih Ping Lin, Chung-Len Lee, Jwu E. Chen
2005	—	`conf`	Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. Asian Test Symposium Shih Ping Lin, Chung-Len Lee, Jwu E. Chen
2005	—	`conf`	Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen
2005	—	`conf`	Multilevel full-chip routing with testability and yield enhancement. SLIP Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen
2005	—	`conf`	Oscillation ring based interconnect test scheme for SOC. ASP-DAC Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2004	—	`conf`	A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. Asian Test Symposium Guan-Xun Chen, Chung-Len Lee, Jwu E. Chen
2004	—	`conf`	A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2003	J	`jnl`	Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. J. Inf. Sci. Eng. Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
2002	—	`conf`	A Low Power High Speed Class-B Buffer Amplifier for Flat Panel Display Application. DELTA Chih-Wen Lu, Chung-Len Lee
2002	—	`conf`	A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. Asian Test Symposium Ming Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen
2002	J	`jnl`	A low-power high-speed class-AB buffer amplifier for flat-panel-display application. IEEE Trans. Very Large Scale Integr. Syst. Chih-Wen Lu, Chung-Len Lee
2002	A	`conf`	An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. DATE Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen
2002	J	`jnl`	Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. J. Electron. Test. Chih-Wen Lu, Chung-Len Lee, Chauchin Su, Jwu-E Chen
2002	J	`jnl`	Structural Fault Based Specification Reduction for Testing Analog Circuits. J. Electron. Test. Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
2001	—	`conf`	A computer aided engineering system for memory BIST. ASP-DAC Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee
2001	J	`jnl`	Fault Diagnosis for Linear Analog Circuits. J. Electron. Test. Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2000	J	`jnl`	A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su
2000	—	`conf`	A methodology for fault model development for hierarchical linear systems. Asian Test Symposium Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su
2000	A	`conf`	All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. DATE Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee
2000	—	`conf`	Fault diagnosis for linear analog circuits. Asian Test Symposium Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2000	—	`conf`	Is IDDQ testing not applicable for deep submicron VLSI in year 2011? Asian Test Symposium Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen
2000	J	`jnl`	Oscillation Ring Delay Test for High Performance Microprocessors. J. Electron. Test. Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir
1999	J	`jnl`	A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model. J. Inf. Sci. Eng. Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen
1999	—	`conf`	Analog Metrology and Stimulus Selection in a Noisy Environment. Asian Test Symposium Chauchin Su, Yue-Tsang Chen, Chung-Len Lee
1998	J	`jnl`	A Two-Phase Fault Simulation Scheme for Sequential Circuits. J. Inf. Sci. Eng. Wen Ching Wu, Chung-Len Lee, Jwu E. Chen
1998	A	`conf`	Maximization of power dissipation under random excitation for burn-in testing. ITC Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen
1998	Misc	`conf`	Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. VTS Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
1997	—	`conf`	Fault diagnosis of odd-even sorting networks. Asian Test Symposium Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen
1997	Misc	`conf`	Functional test pattern generation for CMOS operational amplifier. VTS Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
1997	J	`jnl`	Identifying invalid states for sequential circuit test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
1996	J	`jnl`	A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines. IEEE Trans. Computers Chung-Len Lee, Meng-Lieh Sheu
1996	—	`conf`	Invalid State Identification for Sequential Circuit Test Generation. Asian Test Symposium Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
1995	—	`conf`	A programmable multiple-sequence generator for BIST applications. Asian Test Symposium Meng-Lieh Sheu, Chung-Len Lee
1995	—	`conf`	Factorization of Multi-Valued Logic Functions. ISMVL Hui Min Wang, Chung-Len Lee, Jwu E. Chen
1995	—	`conf`	Fanout fault analysis for digital logic circuits. Asian Test Symposium Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen
1995	—	`conf`	Identification of robust untestable path delay faults. Asian Test Symposium Wen Ching Wu, Chung-Len Lee, Jwu E. Chen
1995	J	`jnl`	Identifying Untestable Faults in Sequential Circuits. IEEE Des. Test Comput. Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
1995	J	`jnl`	Universal test set generation for CMOS circuits. J. Electron. Test. Beyin Chen, Chung-Len Lee
1994	J	`jnl`	A complement-based fast algorithm to generate universal test sets for multi-output functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Beyin Chen, Chung-Len Lee
1994	—	`conf`	Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. ISMVL Hui Min Wang, Chung-Len Lee, Jwu E. Chen
1994	—	`conf`	Complete Test Set for Multiple-Valued Logic Networks. ISMVL Hui Min Wang, Chung-Len Lee, Jwu E. Chen
1994	—	`conf`	Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. EDAC-ETC-EUROASIC Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin
1994	J	`jnl`	Simplifying Sequential Circuit Test Generation. IEEE Des. Test Comput. Meng-Lieh Sheu, Chung-Len Lee
1994	—	`conf`	TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. EDAC-ETC-EUROASIC Meng Chiy Lin, Jwu E. Chen, Chung-Len Lee
1992	—	`conf`	Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. ISMVL Hui Min Wang, Chung-Len Lee, Jwu E. Chen
1991	J	`jnl`	Checkpoints in irredundant two-level combinational circuits. J. Electron. Test. Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
1991	J	`jnl`	Single-fault fault-collapsing analysis in sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
1990	A	`conf`	Single-fault fault collapsing analysis in sequential logic circuits. ITC Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen