Chung-Len Lee

15 papers A* 1C 1Misc 1Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2014 J jnl
A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor.
IEEE Trans. Very Large Scale Integr. Syst.
Chung-Yi Li, Chung-Len Lee, Ming-Hong Hu, Hwai-Pwu Chou
2011 J jnl
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design.
IEICE Trans. Electron.
Li-Rong Wang, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee
2008 — conf
A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application.
DELTA
Jian Ruan, Chung-Len Lee
2008 C conf
A reconfigurable MAC architecture implemented with mixed-Vt standard cell library.
ISCAS
Li-Rong Wang, Yi-Wei Chiu, Chia-Lin Hu, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee
2005 — conf
Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle.
Asian Test Symposium
Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu
2005 J jnl
Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults.
IEEE Des. Test Comput.
Ming Shae Wu, Chung-Len Lee
2004 — conf
A New Path Delay Test Scheme Based on Path Delay Inertia.
Asian Test Symposium
Chung Liang Chen, Chung-Len Lee, Ming Shae Wu
2003 — conf
An On-Chip Jitter Measurement Circuit for the PLL.
Asian Test Symposium
Chin-Cheng Tsai, Chung-Len Lee
2001 Misc conf
Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment.
VTS
Tek Jau Tan, Chung-Len Lee
2000 J jnl
Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.
J. Inf. Sci. Eng.
Hsing-Chung Liang, Chung-Len Lee
1999 — conf
An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.
Asian Test Symposium
Hsing-Chung Liang, Chung-Len Lee
1995 — conf
On Designing of 4-Valued Memory with Double-Gate TFT.
ISMVL
Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang
1995 — conf
Panel: New Research Problems in the Emerging Test Technology.
Asian Test Symposium
Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, Parimal Pal Chaudhuri
1994 — conf
Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic.
ISMVL
Yeong-Jar Chang, Chung-Len Lee
1991 A* conf
A Probabilistic Testability Measure for Delay Faults.
DAC
Wen Ching Wu, Chung-Len Lee