Chung-Kuan Cheng

323 papers A* 36A 37B 1C 20Misc 1Journal 108Unranked 118
YearRankTypeTitle / Venue / Authors
2026 J jnl
An Extended Study of Gear-Ratio-Aware Standard Cell Layout Generation for DTCO Exploration.
CoRR
Chung-Kuan Cheng, Andrew B. Kahng, Bill Lin, Yucheng Wang, Dooseok Yoon
2025 A conf
(Invited Paper) Overview of 2025 CAD Contest at ICCAD.
ICCAD
Chung-Kuan Cheng, Shao-Yun Fang, Yi-Yu Liu, Tsun-Ming Tseng
2025 — conf
Cell-Flex Metrics for Designing Optimal Standard Cell Layout with Enhanced Cell Layout Flexibility.
ISPD
Byeonggon Kang, Ying Yuan, Yucheng Wang, Bill Lin, Chung-Kuan Cheng
2025 — conf
Invited: Scaling Standard Cell Layout Using Track Height Compression and Design Technology Co-optimization.
ISPD
Chung-Kuan Cheng, Byeonggon Kang, Bill Lin, Yucheng Wang
2025 A conf
SO3-Cell: Standard Cell Layout Automation Framework for Simultaneous Optimization of Topology, Placement, and Routing.
ICCAD
Chung-Kuan Cheng, Andrew B. Kahng, Byeonggon Kang, Seokhyeong Kang, Jakang Lee, Bill Lin
2025 — conf
Standard Cell Layout Generation: Review, Challenges, and Future Works.
ASP-DAC
Chung-Kuan Cheng, Byeonggon Kang, Bill Lin, Yucheng Wang
2024 A* conf
Continuous Partitioning for Graph-Based Semi-Supervised Learning.
NeurIPS
Chester Holtz, Pengwen Chen, Zhengchao Wan, Chung-Kuan Cheng, Gal Mishne
2024 — conf
Noise-Aware Circuit Clustering based on Analytical Placement Evolution.
SLIP
Zhiyuan Chen, Chung-Kuan Cheng, Zhan Song, Yucheng Wang
2024 J jnl
On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations.
CoRR
Chester Holtz, Yucheng Wang, Chung-Kuan Cheng, Bill Lin
2024 A conf
Overview of 2024 CAD contest at ICCAD.
ICCAD
Shao-Yun Fang, Yi-Yu Liu, Chung-Kuan Cheng, Tsun-Ming Tseng
2024 A conf
SMT-based Layout Synthesis for Silicon-based Quantum Computing with Crossbar Architecture.
ICCAD
Sheng-Tan Huang, Ying-Jie Jiang, Shao-Yun Fang, Chung-Kuan Cheng
2023 — conf
Assessment of Reinforcement Learning for Macro Placement.
ISPD
Chung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, Zhiang Wang
2023 J jnl
Assessment of Reinforcement Learning for Macro Placement.
CoRR
Chung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, Zhiang Wang
2023 J jnl
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.
ACM Trans. Design Autom. Electr. Syst.
Chung-Kuan Cheng, Chester Holtz, Andrew B. Kahng, Bill Lin, Uday Mallappa
2023 — conf
Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration.
SLIP
Chung-Kuan Cheng, Andrew B. Kahng, Bill Lin, Yucheng Wang, Dooseok Yoon
2023 — conf
Invited Paper: The Scope and Challenges of Scaling in Advanced Technologies.
SLIP
Chung-Kuan Cheng, Bill Lin, Byeonggon Kang, Yucheng Wang
2023 — conf
Placement Initialization via Sequential Subspace Optimization with Sphere Constraints.
ISPD
Pengwen Chen, Chung-Kuan Cheng, Albert Chern, Chester Holtz, Aoxi Li, Yucheng Wang
2023 J jnl
Semi-Supervised Laplacian Learning on Stiefel Manifolds.
CoRR
Chester Holtz, Pengwen Chen, Alexander Cloninger, Chung-Kuan Cheng, Gal Mishne
2023 J jnl
Using EEG Signals to Assess Workload during Memory Retrieval in a Real-world Scenario.
CoRR
Kuan-Jung Chiang, Steven Dong, Chung-Kuan Cheng, Tzyy-Ping Jung
2022 J jnl
JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation.
IEEE Des. Test
Uday Mallappa, Chung-Kuan Cheng, Bill Lin
2022 J jnl
Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation.
IEEE Embed. Syst. Lett.
Uday Mallappa, Chung-Kuan Cheng, Bill Lin
2022 J jnl
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Daeyeal Lee, Bill Lin
2022 J jnl
Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform.
IEEE Access
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin
2022 — conf
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization.
ASP-DAC
Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz
2022 J jnl
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization.
CoRR
Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz
2022 J jnl
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Kuan Cheng, Andrew B. Kahng, Hayoung Kim, Minsoo Kim, Daeyeal Lee, Dongwon Park, Mingyu Woo
2022 A* conf
Placement initialization via a projected eigenvector algorithm: late breaking results.
DAC
Pengwen Chen, Chung-Kuan Cheng, Albert Chern, Chester Holtz, Aoxi Li, Yucheng Wang
2022 J jnl
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing.
ACM Trans. Archit. Code Optim.
Daeyeal Lee, Bill Lin, Chung-Kuan Cheng
2021 — conf
A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs.
ASP-DAC
Ting-Chou Lin, Devon J. Merrill, Yen-Yi Wu, Chester Holtz, Chung-Kuan Cheng
2021 J jnl
Arnoldi Algorithms with Structured Orthogonalization.
SIAM J. Numer. Anal.
Pengwen Chen, Chung-Kuan Cheng, Xinyuan Wang
2021 C conf
CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation.
ICCD
Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Minsoo Kim, Daeyeal Lee, Bill Lin, Dongwon Park, Mingyu Woo
2021 J jnl
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT.
IEEE Trans. Very Large Scale Integr. Syst.
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin, Dongwon Park
2021 — conf
Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning.
SLIP
Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Bill Lin
2021 — conf
GRA-LPO: Graph Convolution Based Leakage Power Optimization.
ASP-DAC
Uday Mallappa, Chung-Kuan Cheng
2021 J jnl
SAT-Based On-Track Bus Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
He-Teng Zhang, Masahiro Fujita, Chung-Kuan Cheng, Jie-Hong R. Jiang
2021 J jnl
SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC.
IEEE Embed. Syst. Lett.
Daeyeal Lee, Bill Lin, Chung-Kuan Cheng
2021 J jnl
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Daeyeal Lee, Dongwon Park, Chia-Tung Ho, Ilgweon Kang, Hayoung Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng
2020 A conf
A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT.
ICCAD
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Dongwon Park
2020 J jnl
Arnoldi algorithms with structured orthogonalization.
CoRR
Pengwen Chen, Chung-Kuan Cheng, Xinyuan Wang
2020 — conf
Arrhythmia Classification using Deep Learning and Machine Learning with Features Extracted from Waveform-based Signal Processing.
EMBC
Po-Ya Hsu, Chung-Kuan Cheng
2020 J jnl
Empirical study on sufficient numbers of minimum cuts in strongly connected directed random graphs.
Networks
Eric Chang, Chung-Kuan Cheng, Anushka Gupta, Po-Ya Hsu, Amanda Moffitt, Alissa Ren, Irene Tsaur, Samuel Wang
2020 J jnl
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dongwon Park, Daeyeal Lee, Ilgweon Kang, Chester Holtz, Sicun Gao, Bill Lin, Chung-Kuan Cheng
2020 — conf
R-peak Detection Using a Hybrid of Gaussian and Threshold Sensitivity.
EMBC
Po-Ya Hsu, Chung-Kuan Cheng
2020 — conf
SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm.
ASP-DAC
Dongwon Park, Daeyeal Lee, Ilgweon Kang, Sicun Gao, Bill Lin, Chung-Kuan Cheng
2020 J jnl
Stability and Convergency Exploration of Matrix Exponential Integration on Power Delivery Network Transient Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xinyuan Wang, Pengwen Chen, Chung-Kuan Cheng
2020 C conf
Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility.
ISCAS
Chung-Kuan Cheng, Daeyeal Lee, Dongwon Park
2019 — conf
Cuff-Less Blood Pressure Monitoring with a 3-Axis Accelerometer.
EMBC
Eric Chang, Chung-Kuan Cheng, Anushka Gupta, Po-Han Hsu, Po-Ya Hsu, Hsin-Li Liu, Amanda Moffitt, Alissa Ren, Irene Tsaur, Samuel Wang
2019 — conf
ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques.
ISPD
Dongwon Park, Ilgweon Kang, Yeseong Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng
2019 J jnl
RePlAce: Advancing Solution Quality and Routability Validation in Global Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Lutong Wang
2019 J jnl
Three-dimensional Floorplan Representations by Using Corner Links and Partial Order.
ACM Trans. Design Autom. Electr. Syst.
Ilgweon Kang, Fang Qiao, Dongwon Park, Daniel Kane, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham
2018 — conf
Adaptive sensitivity analysis with nonlinear power load modeling.
SLIP@DAC
Po-Ya Hsu, Chun-Han Yao, Yuwei Wang, Chung-Kuan Cheng
2018 — conf
Fast and precise routability analysis with conditional design rules.
SLIP@DAC
Ilgweon Kang, Dongwon Park, Changho Han, Chung-Kuan Cheng
2018 — conf
Theory and Algorithms of Physical Design.
ISPD
Chung-Kuan Cheng, T. C. Hu, Andrew B. Kahng
2018 A conf
Transient circuit simulation for differential algebraic systems using matrix exponential.
ICCAD
Pengwen Chen, Chung-Kuan Cheng, Dongwon Park, Xinyuan Wang
2018 — conf
Tree Structures and Algorithms for Physical Design.
ISPD
Chung-Kuan Cheng, Ronald L. Graham, Ilgweon Kang, Dongwon Park, Xinyuan Wang
2017 A conf
Exploring the exponential integrators with Krylov subspace algorithms for nonlinear circuit simulation.
ICCAD
Xinyuan Wang, Hao Zhuang, Chung-Kuan Cheng
2017 — conf
Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond.
ISPD
Ilgweon Kang, Chung-Kuan Cheng
2016 — conf
3D floorplan representations: Corner links and partial order.
3DIC
Fang Qiao, Ilgweon Kang, Daniel Kane, Fung Yu Young, Chung-Kuan Cheng, Ronald L. Graham
2016 J jnl
A fast time-domain EM-TCAD coupled simulation framework via matrix exponential with stiffness reduction.
Int. J. Circuit Theory Appl.
Quan Chen, Wim Schoenmaker, Shih-Hung Weng, Chung-Kuan Cheng, Guan-Hua Chen, Lijun Jiang, Ngai Wong
2016 J jnl
An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qinggao Mei, Wim Schoenmaker, Shih-Hung Weng, Hao Zhuang, Chung-Kuan Cheng, Quan Chen
2016 J jnl
Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts, Chung-Kuan Cheng
2016 — conf
ePlace-3D: Electrostatics based Placement for 3D-ICs.
ISPD
Jingwei Lu, Hao Zhuang, Ilgweon Kang, Pengwen Chen, Chung-Kuan Cheng
2015 J jnl
An Algorithmic Framework for Efficient Large-Scale Circuit Simulation Using Exponential Integrators.
CoRR
Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng
2015 A* conf
An algorithmic framework for efficient large-scale circuit simulation using exponential integrators.
DAC
Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng
2015 — conf
An interdigitated non-contact ECG electrode for impedance compensation and signal restoration.
BioCAS
Jeng-Hau Lin, Hao Liu, Chia-Hung Liu, Phillip Lam, Gung-Yu Pan, Hao Zhuang, Ilgweon Kang, Patrick P. Mercier, Chung-Kuan Cheng
2015 — conf
Developing an online steady-state visual evoked potential-based brain-computer interface system using EarEEG.
EMBC
Yu-Te Wang, Masaki Nakanishi, Simon Lind Kappel, Preben Kidmose, Danilo P. Mandic, Yijun Wang, Chung-Kuan Cheng, Tzyy-Ping Jung
2015 J jnl
MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks.
CoRR
Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng
2015 — conf
Power line communication for hybrid power/signal pin SOC design.
SLIP
Xiang Zhang, Yang Liu, Ryan Coutts, Chung-Kuan Cheng
2015 J jnl
Simulation Algorithms with Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks.
CoRR
Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts, Jingwei Lu, Chung-Kuan Cheng
2015 J jnl
ePlace-3D: Electrostatics based Placement for 3D-ICs.
CoRR
Jingwei Lu, Hao Zhuang, Ilgweon Kang, Pengwen Chen, Chung-Kuan Cheng
2015 J jnl
ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis J.-H. Huang, Yufeng Luo, Chin-Chi Teng, Chung-Kuan Cheng
2015 J jnl
ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method.
ACM Trans. Design Autom. Electr. Syst.
Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng
2014 J jnl
Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst.
Shih-Hung Weng, Yulei Zhang, James F. Buckwalter, Chung-Kuan Cheng
2014 A* conf
MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks.
DAC
Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng
2014 J jnl
Worst Case Noise Prediction With Nonzero Current Transition Times for Power Grid Planning.
IEEE Trans. Very Large Scale Integr. Syst.
Xiang Hu, Peng Du, Shih-Hung Weng, Chung-Kuan Cheng
2014 — conf
Worst-case noise area prediciton of on-chip power distribution network.
SLIP
Xiang Zhang, Jingwei Lu, Yang Liu, Chung-Kuan Cheng
2014 A* conf
ePlace: Electrostatics Based Placement Using Nesterov's Method.
DAC
Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis J.-H. Huang, Chin-Chi Teng, Chung-Kuan Cheng
2013 — conf
Developing stimulus presentation on mobile devices for a truly portable SSVEP-based BCI.
EMBC
Yu-Te Wang, Yijun Wang, Chung-Kuan Cheng, Tzyy-Ping Jung
2013 — conf
Empirical mode decomposition improves detection of SSVEP.
EMBC
Liya Huang, Xiaoxia Huang, Yu-Te Wang, Yijun Wang, Tzyy-Ping Jung, Chung-Kuan Cheng
2013 J jnl
FFTPL: An Analytic Placement Algorithm Using Fast Fourier Transform for Density Equalization.
CoRR
Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng
2013 — conf
FFTPL: An analytic placement algorithm using fast fourier transform for density equalization.
ASICON
Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng
2013 — conf
Layer minimization in escape routing for staggered-pin-array PCBs.
ASP-DAC
Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng
2013 J jnl
Modeling and Analysis of Power Distribution Networks in 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst.
Xiang Hu, Peng Du, James F. Buckwalter, Chung-Kuan Cheng
2013 J jnl
Power Grid Simulation using Matrix Exponential Method with Rational Krylov Subspaces.
CoRR
Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng
2013 — conf
Power grid simulation using matrix exponential method with rational Krylov subspaces.
ASICON
Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng
2013 — conf
Worst-case noise prediction using power network impedance profile.
SLIP
Xiang Zhang, Yang Liu, Chung-Kuan Cheng
2012 J jnl
A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Quan Chen, Shih-Hung Weng, Chung-Kuan Cheng
2012 J jnl
A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong
2012 A conf
A fast time-domain EM-TCAD coupled simulation framework via matrix exponential.
ICCAD
Quan Chen, Wim Schoenmaker, Shih-Hung Weng, Chung-Kuan Cheng, Guan-Hua Chen, Lijun Jiang, Ngai Wong
2012 — conf
An on-chip global broadcast network design with equalized transmission lines in the 1024-core era.
SLIP
Guang Sun, Shih-Hung Weng, Chung-Kuan Cheng, Bill Lin, Lieguang Zeng
2012 — conf
Cell-phone based Drowsiness Monitoring and Management system.
BioCAS
Yu-Te Wang, Chung-Kuan Cheng, Kuan-Chih Huang, Chin-Teng Lin, Yijun Wang, Tzyy-Ping Jung
2012 — conf
Character design and stamp algorithms for Character Projection Electron-Beam Lithography.
ASP-DAC
Peng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald L. Graham
2012 A conf
Circuit simulation via matrix exponential method for stiffness handling and parallel processing.
ICCAD
Shih-Hung Weng, Quan Chen, Ngai Wong, Chung-Kuan Cheng
2012 J jnl
Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong
2012 — conf
Globally stable, highly parallelizable fast transient circuit simulation via faber series.
NEWCAS
Ying-Chi Li, Quan Chen, Shih-Hung Weng, Chung-Kuan Cheng, Ngai Wong
2012 — conf
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph.
ISPD
Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng
2012 — conf
Measuring Steady-State Visual Evoked Potentials from non-hair-bearing areas.
EMBC
Yu-Te Wang, Yijun Wang, Chung-Kuan Cheng, Tzyy-Ping Jung
2012 J jnl
Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shih-Hung Weng, Quan Chen, Chung-Kuan Cheng
2011 A conf
A block-diagonal structured model reduction scheme for power grid networks.
DATE
Zheng Zhang, Xiang Hu, Chung-Kuan Cheng, Ngai Wong
2011 C conf
A fast and stable explicit integration method by matrix exponential operator for large scale circuit simulation.
ISCAS
Shih-Hung Weng, Peng Du, Chung-Kuan Cheng
2011 J jnl
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham
2011 — conf
Circuit simulation using matrix exponential method.
ASICON
Shih-Hung Weng, Quan Chen, Chung-Kuan Cheng
2011 — conf
Exploring 3D power distribution network physics.
ASICON
Xiang Hu, Peng Du, Chung-Kuan Cheng
2011 — conf
Linear Dropout Regulator based power distribution design under worst loading.
ASICON
Amirali Shayan Arani, Xiang Hu, Chung-Kuan Cheng, Wenjian Yu, Christopher Pan
2011 — conf
More realistic power grid verification based on hierarchical current and power constraints.
ISPD
Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang, Yuanzhe Wang, Ngai Wong
2011 J jnl
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals.
IEEE Trans. Very Large Scale Integr. Syst.
Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng
2011 — conf
Placement and beyond in honor of Ernest S. Kuh.
ISPD
Chung-Kuan Cheng
2011 — conf
Power grid sizing via convex programming.
ASICON
Peng Du, Shih-Hung Weng, Xiang Hu, Chung-Kuan Cheng
2011 J jnl
Prediction and Comparison of High-Performance On-Chip Global Interconnection.
IEEE Trans. Very Large Scale Integr. Syst.
Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng
2010 — conf
An adaptive parallel flow for power distribution network simulation using discrete Fourier transform.
ASP-DAC
Xiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan Arani, Chung-Kuan Cheng
2010 — conf
Bus via reduction based on floorplan revising.
ACM Great Lakes Symposium on VLSI
Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng
2010 J jnl
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness.
ACM Trans. Design Autom. Electr. Syst.
Renshen Wang, Evangeline F. Y. Young, Chung-Kuan Cheng
2010 J jnl
Efficient Power Network Analysis with Modeling of Inductive Effects.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shan Zeng, Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng
2010 — conf
Enabling power distribution network analysis flows for 3D ICs.
3DIC
Xiang Hu, Thomas Toms, Riko Radojcic, Matt Nowak, Nick Yu, Chung-Kuan Cheng
2010 — conf
On-chip power network optimization with decoupling capacitors and controlled-ESRs.
ASP-DAC
Wanping Zhang, Ling Zhang, Amirali Shayan Arani, Wenjian Yu, Xiang Hu, Zhi Zhu, A. Ege Engin, Chung-Kuan Cheng
2010 — conf
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling.
SLIP
Yulei Zhang, James F. Buckwalter, Chung-Kuan Cheng
2010 — conf
Physical synthesis of bus matrix for high bandwidth low power on-chip communications.
ISPD
Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng
2010 — conf
Worst-case noise prediction with non-zero current transition times for early power distribution system verification.
ISQED
Peng Du, Xiang Hu, Shih-Hung Weng, Amirali Shayan Arani, Xiaoming Chen, A. Ege Engin, Chung-Kuan Cheng
2010 — conf
Worst-case performance prediction under supply voltage and temperature variation.
SLIP
Chung-Kuan Cheng, Andrew B. Kahng, Kambiz Samadi, Amirali Shayan Arani
2009 C conf
3D stacked power distribution considering substrate coupling.
ICCD
Amirali Shayan Arani, Xiang Hu, Wanping Zhang, Chung-Kuan Cheng, A. Ege Engin, Xiaoming Chen, Mikhail Popovich
2009 J jnl
Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design.
IEICE Trans. Electron.
Wenjian Yu, Rui Shi, Chung-Kuan Cheng
2009 C conf
Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders.
IEEE Symposium on Computer Arithmetic
Chung-Kuan Cheng
2009 — conf
Design methodology of high performance on-chip global interconnect using terminated transmission-line.
ISQED
Yulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
2009 J jnl
Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng
2009 J jnl
Efficient Power Network Analysis Considering Multidomain Clock Gating.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng
2009 — conf
Efficient power network analysis with complete inductive modeling.
ISQED
Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng
2009 J jnl
Energy and switch area optimizations for FPGA global routing architectures.
ACM Trans. Design Autom. Electr. Syst.
Yi Zhu, Yuanfang Hu, Michael B. Taylor, Chung-Kuan Cheng
2009 J jnl
Enhancing Learning Effectiveness in Digital Design Courses Through the Use of Programmable Logic Boards.
IEEE Trans. Educ.
Yi Zhu, Thomas Weng, Chung-Kuan Cheng
2009 — conf
High performance on-chip differential signaling using passive compensation for global communication.
ASP-DAC
Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng
2009 A* conf
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
DAC
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng
2009 — conf
Noise minimization during power-up stage for a multi-domain power network.
ASP-DAC
Wanping Zhang, Yi Zhu, Wenjian Yu, Amirali Shayan Arani, Renshen Wang, Zhi Zhu, Chung-Kuan Cheng
2009 — conf
Octilinear redistributive routing in bump arrays.
ACM Great Lakes Symposium on VLSI
Renshen Wang, Chung-Kuan Cheng
2009 — conf
On the bound of time-domain power supply noise based on frequency-domain target impedance.
SLIP
Xiang Hu, Wenbo Zhao, Peng Du, Yulei Zhang, Amirali Shayan Arani, Christopher Pan, A. Ege Engin, Chung-Kuan Cheng
2009 — conf
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design.
ACM Great Lakes Symposium on VLSI
Renshen Wang, Chung-Kuan Cheng
2009 — conf
Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network.
ISQED
Amirali Shayan Arani, Xiang Hu, He Peng, Wenjian Yu, Wanping Zhang, Chung-Kuan Cheng, Mikhail Popovich, Xiaoming Chen, Lew Chua-Eoan, Xiaohua Kong
2009 — conf
Parallel transistor level circuit simulation using domain decomposition methods.
ASP-DAC
He Peng, Chung-Kuan Cheng
2009 A conf
Parallel transistor level full-chip circuit simulation.
DATE
He Peng, Chung-Kuan Cheng
2009 — conf
Predicting the worst-case voltage violation in a 3D power network.
SLIP
Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng
2009 — conf
Prediction of high-performance on-chip global interconnection.
SLIP
Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng
2009 A conf
Reliability aware through silicon via planning for 3D stacked ICs.
DATE
Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kuan Cheng, Wenjian Yu, Mikhail Popovich, Thomas Toms, Xiaoming Chen
2009 C conf
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations.
ICCD
Renshen Wang, Takumi Okamoto, Chung-Kuan Cheng
2009 — ed.
The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings
SLIP
Chung-Kuan Cheng, Sherief Reda
2008 — conf
3-D floorplanning using labeled tree and dual sequences.
ISPD
Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng
2008 A conf
A novel fixed-outline floorplanner with zero deadspace for hierarchical design.
ICCAD
Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng
2008 A conf
Advancing supercomputer performance through interconnection topology synthesis.
ICCAD
Yi Zhu, Michael B. Taylor, Scott B. Baden, Chung-Kuan Cheng
2008 J jnl
Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng
2008 J jnl
Analyzing High-Density ECG Signals Using ICA.
IEEE Trans. Biomed. Eng.
Yi Zhu, Amirali Shayan Arani, Wanping Zhang, Tong Lee Chen, Tzyy-Ping Jung, Jeng-Ren Duann, Scott Makeig, Chung-Kuan Cheng
2008 — conf
Clock Skew Analysis via Vector Fitting in Frequency Domain.
ISQED
Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, Chung-Kuan Cheng
2008 A conf
Efficient and accurate eye diagram prediction for high speed signaling.
ICCAD
Rui Shi, Wenjian Yu, Yi Zhu, Chung-Kuan Cheng, Ernest S. Kuh
2008 A conf
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.
DATE
Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng
2008 — conf
High performance current-mode differential logic.
ASP-DAC
Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto
2008 — conf
Low Power Passive Equalizer Design for Computer Memory Links.
Hot Interconnects
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
2008 A* conf
Low power passive equalizer optimization using tritonic step response.
DAC
Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng
2008 C conf
On-chip high performance signaling using passive compensation.
ICCD
Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng
2008 — conf
Timing-power optimization for mixed-radix Ling adders by integer linear programming.
ASP-DAC
Yi Zhu, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng
2007 — conf
An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization.
ASP-DAC
Haikun Zhu, Yi Zhu, Chung-Kuan Cheng, David M. Harris
2007 — conf
Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration.
CICC
Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng
2007 — conf
Approaching Speed-of-light Distortionless Communication for On-chip Interconnect.
ASP-DAC
Haikun Zhu, Rui Shi, Chung-Kuan Cheng, Hongyu Chen
2007 J jnl
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2007 J jnl
Efficient Timing Analysis With Known False Paths Using Biclique Covering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng
2007 C conf
Exploring Cardioneural Signals from Noninvasive ECG Measurement.
BIBE
Amirali Shayan Arani, Yi Zhu, Yi-Ning Cheng, Chung-Kuan Cheng, Shien-Fong Lin, Peng-Sheng Chen
2007 C conf
FPGA global routing architecture optimization using a multicommodity flow approach.
ICCD
Yuanfang Hu, Yi Zhu, Michael B. Taylor, Chung-Kuan Cheng
2007 C conf
Fast Transient Simulation of Lossy Transmission Lines.
ISCAS
He Peng, Chung-Kuan Cheng
2007 C conf
Fast power network analysis with multiple clock domains.
ICCD
Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng
2007 C conf
Incremental Power Impedance Optimization Using Vector Fitting Modeling.
ISCAS
Wanping Zhang, Chung-Kuan Cheng
2007 — conf
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space.
ASP-DAC
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis
2007 C conf
Passive compensation for high performance inter-chip communication.
ICCD
Chun-Chen Liu, Haikun Zhu, Chung-Kuan Cheng
2007 — conf
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals.
ISQED
Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng
2007 J jnl
Two-Stage Newton-Raphson Method for Transistor-Level Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhengyong Zhu, He Peng, Chung-Kuan Cheng, Khosro Rouz, Manjit Borah, Ernest S. Kuh
2006 A conf
An iterative division algorithm for FPGAs.
FPGA
Jianhua Liu, Michael Chang, Chung-Kuan Cheng
2006 — conf
An unconditional stable general operator splitting method for transistor level transient analysis.
ASP-DAC
Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh
2006 A* conf
Communication latency aware low power NoC synthesis.
DAC
Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng
2006 A* conf
Efficient escape routing for hexagonal array of high density I/Os.
DAC
Rui Shi, Chung-Kuan Cheng
2006 — conf
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.
ASP-DAC
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton
2006 J jnl
General Floorplans with L/T-Shaped Blocks Using Corner Block List.
J. Comput. Sci. Technol.
Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
2006 J jnl
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2006 — conf
Integrating dynamic thermal via planning with 3D floorplanning algorithm.
ISPD
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2006 A conf
Layer minimization of escape routing in area array packaging.
ICCAD
Renshen Wang, Rui Shi, Chung-Kuan Cheng
2006 C conf
Noninvasive Study of the Human Heart using Independent Component Analysis.
BIBE
Yi Zhu, Tong Lee Chen, Wanping Zhang, Tzyy-Ping Jung, Jeng-Ren Duann, Scott Makeig, Chung-Kuan Cheng
2006 J jnl
On the construction of zero-deficiency parallel prefix circuits with minimum depth.
ACM Trans. Design Autom. Electr. Syst.
Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham
2006 A conf
Timing model reduction for hierarchical timing analysis.
ICCAD
Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng
2006 J jnl
VLSI Block Placement With Alignment Constraints.
IEEE Trans. Circuits Syst. II Express Briefs
Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng
2005 — conf
A multi-level transmission line network approach for multi-giga hertz clock distribution.
ASP-DAC
Hongyu Chen, Chung-Kuan Cheng
2005 — conf
Buffer Planning Algorithm Based on Partial Clustered Floorplanning.
ISQED
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
2005 J jnl
Buffer planning as an Integral part of floorplanning with consideration of routing congestion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu
2005 — conf
Constructing zero-deficiency parallel prefix adder of minimum depth.
ASP-DAC
Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham
2005 — conf
Efficient transient simulation for transistor-level analysis.
ASP-DAC
Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh
2005 — conf
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.
ISQED
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
2005 A conf
Improving the efficiency of static timing analysis with false paths.
ICCAD
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
2005 — conf
Integrated algorithmic logical and physical design of integer multiplier.
ASP-DAC
Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng
2005 — conf
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
ASP-DAC
Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
2005 — conf
Performance constrained floorplanning based on partial clustering [IC layout].
ISCAS (2)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
2005 C conf
Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz.
ICCD
Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng
2005 C conf
Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications.
ICCD
Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris
2005 J jnl
The Y architecture for on-chip interconnect: analysis and methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
2005 — conf
Unified quadratic programming approach for mixed mode placement.
ISPD
Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris
2005 — conf
VLSI block placement with alignment constraints based on corner block list.
ISCAS (6)
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
2004 J jnl
A buffer planning algorithm for chip-level floorplanning.
Sci. China Ser. F Inf. Sci.
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 — conf
A buffer planning algorithm with congestion optimization.
ASP-DAC
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 — conf
A multiple level network approach for clock skew minimization with process variations.
ASP-DAC
Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng
2004 J jnl
Area minimization of power distribution network using efficient nonlinear programming techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
2004 — conf
Buffer allocation algorithm with consideration of routing congestion.
ASP-DAC
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 J jnl
Corner block list representation and its application to floorplan optimization.
IEEE Trans. Circuits Syst. II Express Briefs
Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 J jnl
Corner block list representation and its application with boundary constraints.
Sci. China Ser. F Inf. Sci.
Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 J jnl
Fast Evaluation of Bounded Slice-Line Grid.
J. Comput. Sci. Technol.
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu
2004 A conf
Fast adders in modern FPGAs.
FPGA
Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris
2004 J jnl
Fast postplacement optimization using functional symmetries.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen
2004 — ch.
Floorplan Representation in VLSI.
Handbook of Data Structures and Applications
Zhou Feng, Bo Yao, Chung-Kuan Cheng
2004 — conf
Optimal planning for mesh-based power distribution.
ASP-DAC
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang
2004 J jnl
Stairway compaction using corner block list and its applications with rectilinear blocks.
ACM Trans. Design Autom. Electr. Syst.
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 J jnl
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu
2003 — conf
A buffer planning algorithm based on dead space redistribution.
ASP-DAC
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003 — conf
A hierarchical three-way interconnect architecture for hexagonal processors.
SLIP
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham
2003 A conf
An Algorithmic Approach for Generic Parallel Adders.
ICCAD
Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng
2003 A* conf
An algebraic multigrid solver for analytical placement with layout based clustering.
DAC
Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
2003 — conf
An integrated floorplanning with an efficient buffer planning algorithm.
ISPD
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003 — conf
Arbitrary convex and concave rectilinear block packing based on corner block list.
ISCAS (5)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu
2003 A* conf
Dynamic global buffer planning optimization based on detail block locating and congestion analysis.
DAC
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003 — conf
Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing.
SLIP
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang
2003 — conf
Evaluating a bounded slice-line grid assignment in O(nlogn) time.
ISCAS (4)
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003 J jnl
Floorplan representations: Complexity and connections.
ACM Trans. Design Autom. Electr. Syst.
Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham
2003 A* conf
Power network analysis using an adaptive algebraic multigrid approach.
DAC
Zhengyong Zhu, Bo Yao, Chung-Kuan Cheng
2003 — conf
RCLK-VJ network reduction with Hurwitz polynomial approximation.
ASP-DAC
Zhanhai Qin, Chung-Kuan Cheng
2003 A* conf
Realizable parasitic reduction using generalized Y-Delta transformation.
DAC
Zhanhai Qin, Chung-Kuan Cheng
2003 A conf
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology.
ICCAD
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
2003 — conf
The Y-architecture: yet another on-chip interconnect solution.
ASP-DAC
Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng
2003 — conf
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing.
ASP-DAC
Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu
2002 J jnl
An Optimum Placement Search Algorithm Based on Extended Corner Block List.
J. Comput. Sci. Technol.
Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai
2002 C conf
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power.
ICCD
Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham
2002 C conf
Physical Planning Of On-Chip Interconnect Architectures.
ICCD
Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng
2002 — conf
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction.
SLIP
Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng
2002 — conf
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks.
ASP-DAC/VLSI Design
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2002 J jnl
Toward better wireload models in the presence of obstacles.
IEEE Trans. Very Large Scale Integr. Syst.
Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt
2001 A conf
Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques.
ICCAD
Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
2001 — conf
ECBL: an extended corner block list with solution space including optimum placement.
ISPD
Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
2001 J jnl
Floorplanning using a tree representation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, Takeshi Yoshimura
2001 A* conf
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.
DAC
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001 J jnl
Floorplanning with abutment constraints based on corner block list.
Integr.
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001 — conf
Interconnect implications of growth-based structural models for VLSI circuits.
SLIP
Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu
2001 — conf
Rectilinear block packing using O-tree representation.
ISPD
Yingxin Pang, Chung-Kuan Cheng, Koen Lampaert, Weize Xie
2001 — conf
Revisiting floorplan representations.
ISPD
Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham
2001 — conf
Toward better wireload models in the presence of obstacles.
ASP-DAC
Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt
2001 — conf
VLSI floorplanning with boundary constraints based on corner block list.
ASP-DAC
Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2000 — conf
A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation.
ASP-DAC
Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng
2000 — conf
An enhanced perturbing algorithm for floorplan design using the O-tree representation.
ISPD
Yingxin Pang, Chung-Kuan Cheng, Takeshi Yoshimura
2000 A* conf
Block placement with symmetry constraints based on the O-tree non-slicing representation.
DAC
Yingxin Pang, Florin Balasa, Koen Lampaert, Chung-Kuan Cheng
2000 A conf
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan.
ICCAD
Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
2000 A* conf
Fast post-placement rewiring using easily detectable functional symmetries.
DAC
Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska
2000 A conf
Hurwitz Stable Reduced Order Modelling for RLC Interconnect Trees.
ICCAD
Xiaodong Yang, Chung-Kuan Cheng, Walter H. Ku, Robert J. Carragher
2000 J jnl
Tutorial on VLSI Partitioning.
VLSI Design
Sao-Jie Chen, Chung-Kuan Cheng
1999 — conf
A Performance-Driven I/O Pin Routing Algorithm.
ASP-DAC
Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arunabha Sen
1999 A* conf
An O-Tree Representation of Non-Slicing Floorplan and Its Applications.
DAC
Pei-Ning Guo, Chung-Kuan Cheng, Takeshi Yoshimura
1999 J jnl
Empirical Study of Block Placement by Cluster Refinement.
VLSI Design
Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
1999 A conf
RLC interconnect delay estimation via moments of amplitude and phase response.
ICCAD
Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng
1999 J jnl
Sequence-pair approach for rectilinear module placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
1999 J jnl
Timing optimization for multisource nets: characterization andoptimal repeater insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
John Lillis, Chung-Kuan Cheng
1998 A* conf
Extending Moment Computation to 2-Port Circuit Representations.
DAC
Fang-Jou Liu, Chung-Kuan Cheng
1998 — conf
Rectilinear block placement using sequence-pair.
ISPD
Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
1998 J jnl
Routability improvement using dynamic interconnect architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Jianmin Li, Chung-Kuan Cheng
1997 A* conf
A Network Flow Approach for Hierarchical Tree Partitioning.
DAC
Ming-Ter Kuo, Chung-Kuan Cheng
1997 — conf
A building block placement tool.
ASP-DAC
Jonathan Dufour, Robert McBride, Ping Zhang, Chung-Kuan Cheng
1997 — conf
A new layout-driven timing model for incremental layout optimization.
ASP-DAC
Fang-Jou Liu, John Lillis, Chung-Kuan Cheng
1997 A* conf
Cluster Refinement for Block Placement.
DAC
Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
1997 J jnl
TIGER: an efficient timing-driven global router for gate array and standard cell layout design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
1997 A* conf
Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion.
DAC
John Lillis, Chung-Kuan Cheng
1996 J jnl
A global router with a theoretical bound on the optimal solution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Robert C. Carden IV, Jianmin Li, Chung-Kuan Cheng
1996 J jnl
A wire length estimation technique utilizing neighborhood density equations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau
1996 A* conf
Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming.
DAC
Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng
1996 A* conf
Network Partitioning into Tree Hierarchies.
DAC
Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng
1996 A* conf
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing.
DAC
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho
1996 A* conf
New Spectral Linear Placement and Clustering Approach.
DAC
Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng
1996 J jnl
Optimal wire sizing and buffer insertion for low power and a generalized delay model.
IEEE J. Solid State Circuits
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
1996 J jnl
Performance driven bus buffer insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng
1996 — conf
Simultaneous Routing and Buffer Insertion for High Performance Interconnect.
Great Lakes Symposium on VLSI
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
1996 J jnl
Solving the net matching problem in high-performance chip design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong, Masahiro Fujita, Ramamohan Paturi
1995 J jnl
A cell-based hierarchical pitchmatching compaction using minimal LP.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
1995 A conf
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm.
ICCAD
Lung-Tien Liu, Ming-Ter Kuo, Shih-Chen Huang, Chung-Kuan Cheng
1995 J jnl
A replication cut for two-way partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu
1995 J jnl
Circuit clustering using a stochastic flow injection method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
1995 C conf
Finite State Machine Decomposition for I/O Minimization.
ISCAS
Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng
1995 A conf
Linear decomposition algorithm for VLSI design applications.
ICCAD
Jianmin Li, John Lillis, Chung-Kuan Cheng
1995 J jnl
Local ratio cut and set covering partitioning for huge logic emulation systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof
1995 J jnl
On general zero-skew clock net construction.
IEEE Trans. Very Large Scale Integr. Syst.
Nan-Chi Chou, Chung-Kuan Cheng
1995 A conf
Optimal wire sizing and buffer insertion for low power and a generalized delay model.
ICCAD
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
1995 J jnl
Optimization by iterative improvement: an experimental evaluation on two-way partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
1995 — conf
Optimization of power dissipation and skew sensitivity in clock buffer synthesis.
ISLPD
Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin
1995 — conf
Performance driven multiple-source bus synthesis using buffer insertion.
ASP-DAC
Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin
1995 A* conf
Performance-Driven Partitioning Using a Replication Graph Approach.
DAC
Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu
1995 J jnl
Physical models and algorithms for optoelectronic MCM layout.
IEEE Trans. Very Large Scale Integr. Syst.
Jiao Fan, D. Zaleta, Chung-Kuan Cheng, S. H. Lee
1995 Misc conf
Routability improvement using dynamic interconnect architecture.
FCCM
Jianmin Li, Chung-Kuan Cheng
1995 C conf
Simple tree-construction heuristics for the fanout problem .
ICCD
Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng
1994 J jnl
A general purpose, multiple-way partitioning algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
1994 J jnl
A multi-probe approach for MCM substrate testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu
1994 J jnl
Block-oriented programmable design with switching network interconnect.
IEEE Trans. Very Large Scale Integr. Syst.
Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel
1994 A* conf
Circuit Partitioning for Huge Logic Emulation Systems.
DAC
Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof
1994 A* conf
Data Flow Partitioning for Clock Period and Latency Minimization.
DAC
Lung-Tien Liu, Minshine Shih, Chung-Kuan Cheng
1994 A conf
Skew sensitivity minimization of buffered clock tree.
ICCAD
Jae Chung, Chung-Kuan Cheng
1993 A* conf
An Efficient Timing-Driven Global Routing Algorithm.
DAC
Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh
1993 A conf
An efficient algorithm for the net matching problem.
ICCAD
Robert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita
1993 A* conf
Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP.
DAC
So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
1993 A* conf
Performance-Driven Steiner Tree Algorithm for Global Routing.
DAC
Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang
1993 A conf
Performance-driven partitioning using retiming and replication.
ICCAD
Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku
1992 A* conf
A Wire Length Estimation Technique Utilizing Neighborhood Density Equations.
DAC
Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau
1992 A conf
A probabilistic multicommodity-flow solution to circuit clustering problems.
ICCAD
Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
1992 A conf
An optimal probe testing algorithm for the connectivity verification of MCM substrates.
ICCAD
So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu
1992 A* conf
FARM: An Efficient Feed-Through Pin Assignment Algorithm.
DAC
Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh
1992 J jnl
Geometric compaction on channel routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Kuan Cheng, David N. Deutsch, Craig Shohara, Mark Taparauskas, Mark Bubien
1992 J jnl
Maximum Concurrent Flows and Minimum Cuts.
Algorithmica
Chung-Kuan Cheng, T. C. Hu
1992 J jnl
Symbolic layout compaction under conditional design rules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Kuan Cheng, Xiaotie Deng, Yuh-Zen Liao, So-Zen Yao
1992 J jnl
The optimal partitioning of networks.
Networks
Chung-Kuan Cheng
1991 A* conf
A General Purpose Multiple Way Partitioning Algorithm.
DAC
Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin
1991 A* conf
A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm.
DAC
Robert C. Carden IV, Chung-Kuan Cheng
1991 J jnl
An improved two-way partitioning algorithm with stable performance [VLSI].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Kuan Cheng, Yen-Chuen Wei
1991 J jnl
Ancestor tree for arbitrary multi-terminal cut functions.
Ann. Oper. Res.
Chung-Kuan Cheng, T. C. Hu
1991 J jnl
Multiple-level partitioning: an application to the very large-scale hardware simulator.
IEEE J. Solid State Circuits
Yen-Chuen Wei, Chung-Kuan Cheng, Ze'ev Wurman
1991 J jnl
Ratio cut partitioning for hierarchical designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yen-Chuen Wei, Chung-Kuan Cheng
1991 J jnl
The Orientation of Modules Based on Graph Decomposition.
IEEE Trans. Computers
Chung-Kuan Cheng, So-Zen Yao, T. C. Hu
1990 A conf
A Two-Level Two-Way Partitioning Algorithm.
ICCAD
Yen-Chuen Wei, Chung-Kuan Cheng
1990 B conf
Ancestor Tree for Arbitrary Multi-Terminal Cut Functions.
IPCO
Chung-Kuan Cheng, T. C. Hu
1989 A conf
Towards efficient hierarchical designs by ratio cut partitioning.
ICCAD
Yen-Chuen Wei, Chung-Kuan Cheng
1988 A* conf
Improved Channel Routing by Via Minimization and Shifting.
DAC
Chung-Kuan Cheng, David N. Deutsch
1987 J jnl
Linear placement algorithms and applications to VLSI design.
Networks
Chung-Kuan Cheng
1984 J jnl
Module Placement Based on Resistive Network Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Kuan Cheng, Ernest S. Kuh