Chung-Han Chou

15 papers A 8Journal 4Unranked 3

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Invited Paper: 2025 ICCAD CAD Contest Problem A: Hardware Trojan Detection on Gate-Level Netlist. ICCAD Chung-Han Chou, Chih-Jen (Jacky) Hsu, Hung-Chun Chiu, Kai-Chiang Wu, Yu-Guang Chen, Zhuo Li
2024	A	`conf`	2024 ICCAD CAD Contest Problem A: Reinforcement Logic Optimization for a General Cost Function. ICCAD Chung-Han Chou, Chih-Jen Hsu, Chi-An Wu, Kuan-Hua Tu, Kwangsoo Han, Zhou Li
2023	A	`conf`	Invited Paper: 2023 ICCAD CAD Contest Problem A: Multi-Bit Large-Scale Boolean Matching. ICCAD Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu, Kei-Yong Khoo
2022	A	`conf`	2022 CAD Contest Problem A: Learning Arithmetic Operations from Gate-Level Circuit. ICCAD Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu
2021	A	`conf`	2021 CAD Contest Problem A: Functional ECO with Behavioral Change Guidance Invited Paper. ICCAD Yen-Chun Fang, Shao-Lun Huang, Chi-An Wu, Chung-Han Chou, Chih-Jen Hsu, WoeiTzy Jong, Kei-Yong Khoo
2020	J	`jnl`	Making Aging Useful by Recycling Aging-induced Clock Skew. ACM Trans. Design Autom. Electr. Syst. Tien-Hung Tseng, Chung-Han Chou, Kai-Chiang Wu
2019	—	`conf`	Aging-aware chip health prediction adopting an innovative monitoring strategy. ASP-DAC Yun-Ting Wang, Kai-Chiang Wu, Chung-Han Chou, Shih-Chieh Chang
2018	J	`jnl`	Sensor-Based Time Speculation in the Presence of Timing Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Han Chou, Tsui-Yun Chang, Kai-Chiang Wu, Shih-Chieh Chang
2017	—	`conf`	CN-SIM: A cycle-accurate full system power delivery noise simulator. ASP-DAC Kassan Unda, Chung-Han Chou, Shih-Chieh Chang, Cheng Zhuo, Yiyu Shi
2017	J	`jnl`	Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Han Chou, Yenting Lai, Yi-Chun Chang, Chih-Yu Wang, Liang-Chia Cheng, Shih-Hsu Huang, Shih-Chieh Chang
2016	J	`jnl`	Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. IEEE Trans. Very Large Scale Integr. Syst. Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang
2013	A	`conf`	Low-power timing closure methodology for ultra-low voltage designs. ICCAD Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou
2013	—	`conf`	On the futility of thermal through-silicon-vias. VLSI-DAT Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Yiyu Shi, Jui-Hung Chien, Shih-Chieh Chang
2011	A	`conf`	On the preconditioner of conjugate gradient method - A power grid simulation perspective. ICCAD Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Che-Rung Lee, Yiyu Shi, Shih-Chieh Chang
2010	A	`conf`	Clock skew optimization considering complicated power modes. DATE Chiao-Ling Lung, Zi-Yi Zeng, Chung-Han Chou, Shih-Chieh Chang