Chun-Yu Lin

11 papers Journal 4Unranked 7
YearRankTypeTitle / Venue / Authors
2024 J jnl
An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration.
IEEE J. Solid State Circuits
Chun-Yu Lin, Wei-Han Chen, Yu-Ting Hung, Tun-Ju Wang, Tsung-Hsien Lin
2022 J jnl
A Temperature-Compensated Crystal Oscillator With Piecewise Polynomial Varactor Compensation Achieving ±3.75-ppm Inaccuracy From -30°C to 90°C.
IEEE Trans. Circuits Syst. II Express Briefs
Chun-Yu Lin, Yu-Wei Huang, Tsung-Hsien Lin
2021 — conf
29.5 A 0.008mm
ISSCC
Chun-Yu Lin, Yu-Ting Hung, Tun-Ju Wang, Tsung-Hsien Lin
2021 — conf
A ± 20-ppm -50°C-105°C 1-µA 32.768-kHz Clock Generator with a System-HFXO-Assisted Background Calibration.
A-SSCC
Chun-Yu Lin, Yu-Wei Huang, Tsung-Hsien Lin
2020 — conf
A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique.
VLSI-DAT
Chun-Yu Lin, Tun-Ju Wang, Yu-Ting Hung, Tsung-Hsien Lin
2019 — conf
A 2.4-GHz 500-µW 370-fsrms Integrated Jitter Sub-Sampling Sub-Harmonically Injection-Locked PLL in 90-nm CMOS.
A-SSCC
Chun-Yu Lin, Yu-Ting Hung, Tsung-Hsien Lin
2017 — conf
A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS.
A-SSCC
Chun-Yu Lin, Tun-Ju Wang, Tsung-Hsien Lin
2017 — conf
An ultra-low power 169-nA 32.768-kHz fractional-N PLL.
A-SSCC
Chun-Yu Lin, Tun-Ju Wang, Tzu-Hsuan Liu, Tsung-Hsien Lin
2016 J jnl
A 330-µW 400-MHz BPSK Transmitter in 0.18- µm CMOS for Biomedical Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Yi-Lin Tsai, Chun-Yu Lin, Bang-Cyuan Wang, Tsung-Hsien Lin
2016 — conf
A 4-GHz ΔΣ fractional-N frequency synthesizer with 2-dimensional quantization noise pushing and fractional spur elimination techniques.
A-SSCC
Chun-Yu Lin, Tsung-Hsien Lin
2013 J jnl
A 650-pJ/bit MedRadio Transmitter With an FIR-Embedded Phase Modulator for Medical Micro-Power Networks (MMNs).
IEEE Trans. Circuits Syst. I Regul. Pap.
Yao-Hong Liu, Li-Guang Chen, Chun-Yu Lin, Tsung-Hsien Lin