Chun-Yao Wang

117 papers A* 3A 20B 2C 8Journal 36Unranked 48
YearRankTypeTitle / Venue / Authors
2026 J jnl
Approximate Logic Synthesis for Dot-Inverter Graphs Using Node Merging-Enhanced Genetic Algorithm-Based Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Ting Li, Ihao Chen, Yung-Chih Chen, Chun-Yao Wang
2025 — conf
CNN Model Optimization Using a Hybrid Approach of Genetic Algorithm-based Pruning and Retraining with Knowledge Distillation.
ACM Great Lakes Symposium on VLSI
Kuan-Ling Chou, Cheng-Lung Wang, Yung-Chih Chen, Wuqian Tang, Yi-Ting Li, Shih-Chieh Chang, Chun-Yao Wang
2025 A conf
Dynamic IR-Drop Prediction Through a Multi-Task U-Net with Package Effect Consideration.
DATE
Yu-Hsuan Chen, Yu-Chen Cheng, Yong-Fong Chang, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Peng-Wen Chen, Po-Yu Chen, Hao-Yun Chen, Yung-Chih Chen, Chun-Yao Wang, Shih-Chieh Chang
2025 — conf
IMU-Based Motion Trajectory Reconstruction and Recognition with Dynamic Calibration on Embedded System Platform.
ISQED
Kai-Po Hsu, Tsung-Han Lai, Yi-Ting Li, Wuqian Tang, Yun-Ju Lee, Yung-Chih Chen, Wen-Hsin Chiu, Chun-Yao Wang
2025 A* conf
Real-Time Dynamic IR-drop Prediction for IR ECO.
DAC
Yu-Che Lee, Yu-Hsuan Chen, Yu-Chen Cheng, Yong-Fong Chang, Jia-Wei Lin, Hsun-Wei Pao, Yung-Chih Chen, Yi-Ting Li, Wuqian Tang, Shih-Chieh Chang, Chun-Yao Wang
2024 J jnl
9-Input Threshold Function Identification Using a New Necessary Condition of Threshold Function.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu-Chuan Yen, Meng-Jing Li, Yi-Ting Li, Yung-Chih Chen, Ihao Chen, Chun-Yao Wang
2024 A conf
A Hybrid Approach to Reverse Engineering on Combinational Circuits.
DATE
Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang
2024 — conf
IR drop Prediction Based on Machine Learning and Pattern Reduction.
ACM Great Lakes Symposium on VLSI
Yong-Fong Chang, Yung-Chih Chen, Yu-Chen Cheng, Shu-Hong Lin, Che-Hsu Lin, Chun-Yuan Chen, Yu-Hsuan Chen, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Shih-Chieh Chang, Yi-Ting Li, Chun-Yao Wang
2024 B conf
LOOPLock 3.0: A Robust Cyclic Logic Locking Approach.
ASPDAC
Pei-Pei Chen, Xiang-Min Yang, Yu-Cheng He, Yung-Chih Chen, Yi-Ting Li, Chun-Yao Wang
2024 — conf
Model Reduction Using a Hybrid Approach of Genetic Algorithm and Rule-based Method.
SOCC
Wuqian Tang, Chuan-Shun Huang, Yung-Chih Chen, Yi-Ting Li, Shih-Chieh Chang, Chun-Yao Wang
2024 — conf
On Construction of Trajectory of Boxer's Punch using a single IMU.
ISPACS
Yu-Cheng Lee, Kai-Po Hsu, Yun-Ju Lee, Yi-Ting Li, Wuqian Tang, Yung-Chih Chen, Wen-Hsin Chiu, Chun-Yao Wang
2023 J jnl
A Constructive Approach for Threshold Function Identification.
ACM Trans. Design Autom. Electr. Syst.
Meng-Jing Li, Yu-Chuan Yen, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang
2023 — conf
A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation.
ISQED
Hsin-Ping Yen, Shiuan-Hau Huang, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang
2023 — conf
A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed Stimuli.
ASP-DAC
Hsiao-Lun Liu, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang
2023 — conf
Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee.
ASP-DAC
Chun-Ting Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang
2023 A conf
Invited Paper: Overview of 2023 CAD Contest at ICCAD.
ICCAD
Takashi Sato, Chun-Yao Wang, Yu-Guang Chen, Tsung-Wei Huang
2022 J jnl
A Don't-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hsiao-Lun Liu, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang
2022 A conf
An Approach to Unlocking Cyclic Logic Locking: LOOPLock 2.0.
ICCAD
Pei-Pei Chen, Xiang-Min Yang, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang
2022 J jnl
Don't Care Computation and De Morgan Transformation for Threshold Logic Network Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chia-Chun Lin, Ciao-Syun Lin, You-Hsuen Tsai, Yung-Chih Chen, Chun-Yao Wang
2022 J jnl
LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiang-Min Yang, Pei-Pei Chen, Hsiao-Yu Chiang, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang
2022 J jnl
Majority Logic Circuit Minimization Using Node Addition and Removal.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chang-Cheng Ko, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang
2022 A conf
Overview of 2022 CAD Contest at ICCAD.
ICCAD
Yu-Guang Chen, Chun-Yao Wang, Tsung-Wei Huang, Takashi Sato
2021 — conf
A General Equivalence Checking Framework for Multivalued Logic.
ASP-DAC
Chia-Chun Lin, Hsin-Ping Yen, Sheng-Hsiu Wei, Pei-Pei Chen, Yung-Chih Chen, Chun-Yao Wang
2021 — conf
An Efficient Approximate Node Merging with an Error Rate Guarantee.
ASP-DAC
Kit Seng Tam, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang
2021 — conf
An IMU-aided Fitness System.
SoCC
Yi-Ting Lin, Chun-Jui Chen, Pei-Yi Kuo, Si-Huei Lee, Chia-Chun Lin, Yun-Ju Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang
2021 — conf
Cluster Tool Performance Analysis using Graph Database.
SoCC
Shiuan-Hau Huang, Hsin-Ping Yen, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang
2021 J jnl
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model.
ACM J. Emerg. Technol. Comput. Syst.
Chia-Cheng Wu, Yi-Hsiang Hu, Chia-Chun Lin, Yung-Chih Chen, Juinn-Dar Huang, Chun-Yao Wang
2021 J jnl
Industry 3.5 to empower smart production for poultry farming and an empirical study for broiler live weight prediction.
Comput. Ind. Eng.
Chun-Yao Wang, Ying-Jen Chen, Chen-Fu Chien
2021 — conf
On Reduction of Computations for Threshold Function Identification.
SoCC
Wen-Chih Hsu, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang
2021 — conf
On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays.
ISQED
Hsin-Tsung Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang
2021 A conf
Overview of 2021 CAD Contest at ICCAD.
ICCAD
Tsung-Wei Huang, Yu-Guang Chen, Chun-Yao Wang, Takashi Sato
2020 A conf
A Convolutional Result Sharing Approach for Binarized Neural Network Inference.
DATE
Ya-Chun Chang, Chia-Chun Lin, Yi-Ting Lin, Yung-Chih Chen, Chun-Yao Wang
2020 — conf
A Dynamic Expansion Order Algorithm for the SAT-based Minimization.
SoCC
Chia-Chun Lin, Kit Seng Tam, Chana-Cheng Ko, Hsin-Ping Yen, Shenz-Hsiu Wei, Yung-Chih Chen, Chun-Yao Wang
2020 J jnl
A New Necessary Condition for Threshold Function Identification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chia-Chun Lin, Chin-Heng Liu, Yung-Chih Chen, Chun-Yao Wang
2020 — conf
IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement.
ISQED
Teng-Chia Wang, Yan-Ping Chang, Chun-Jui Chen, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang
2020 J jnl
LOOPLock: Logic Optimization-Based Cyclic Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hsiao-Yu Chiang, Yung-Chih Chen, De-Xuan Ji, Xiang-Min Yang, Chia-Chun Lin, Chun-Yao Wang
2020 — conf
Rehabilitation System for Limbs using IMUs.
ISQED
Chun-Jui Chen, Yi-Ting Lin, Chia-Chun Lin, Yung-Chih Chen, Yun-Ju Lee, Chun-Yao Wang
2019 — conf
A Glitch Key-Gate for Logic Locking.
SoCC
De-Xuan Ji, Hsiao-Yu Chiang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang
2019 — conf
A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises.
SoCC
Yan-Ping Chang, Teng-Chia Wang, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang
2019 J jnl
Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chin-Heng Liu, Chia-Chun Lin, Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, Shigeru Yamashita
2018 — conf
A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification.
ACM Great Lakes Symposium on VLSI
Chia-Cheng Wu, Tung-Yuan Lee, Yung-An Lai, Hsin-Pei Wang, De-Xuan Ji, Yan-Ping Chang, Teng-Chia Wang, Chin-Heng Liu, Chun-Yao Wang, Yung-Chih Chen
2018 — conf
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays.
ISVLSI
Chia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang, Chun-Yao Wang
2018 A conf
Efficient synthesis of approximate threshold logic circuits with an error rate guarantee.
DATE
Yung-An Lai, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang
2018 A conf
Logic optimization with considering boolean relations.
DATE
Tung-Yuan Lee, Chia-Cheng Wu, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang
2018 J jnl
On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses.
IEEE Trans. Very Large Scale Integr. Syst.
Hsin-Pei Wang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang
2018 — conf
Using range-equivalent circuits for facilitating bounded sequential equivalence checking.
VLSI-DAT
Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin, Chun-Yao Wang
2017 J jnl
A case study on mathematical expression recognition to GPU.
J. Supercomput.
Ying-Chin Lin, Chun-Yao Wang, Jing-Yun Zeng
2017 J jnl
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays.
IEEE Trans. Very Large Scale Integr. Syst.
Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan
2017 — conf
In&Out: Restructuring for threshold logic network optimization.
ISQED
Chia-Chun Lin, Chiao-Wei Huang, Chun-Yao Wang, Yung-Chih Chen
2017 — conf
Majority logic circuits optimisation by node merging.
ASP-DAC
Chun-Che Chung, Yung-Chih Chen, Chun-Yao Wang, Chia-Cheng Wu
2016 J jnl
An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm.
J. Multiple Valued Log. Soft Comput.
Tai-Lin Chen, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen
2016 J jnl
Area-Aware Decomposition for Single-Electron Transistor Arrays.
ACM Trans. Design Autom. Electr. Syst.
Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suman Datta, Vijaykrishnan Narayanan
2016 J jnl
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays.
IEEE Trans. Very Large Scale Integr. Syst.
Ching-Yi Huang, Yun-Jui Li, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
2016 — conf
MajorSat: A SAT solver to majority logic.
ASP-DAC
Yu-Min Chou, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang
2016 J jnl
Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks.
IEEE Trans. Multi Scale Comput. Syst.
Chen-Yu Lin, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Chiou-Ting Hsu
2015 — conf
A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays.
ASP-DAC
Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
2015 C conf
CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction.
ICCD
Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen
2015 J jnl
Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ching-Yi Huang, Zheng-Shan Yu, Yung-Chun Hu, Tung-Chen Tsou, Chun-Yao Wang, Yung-Chih Chen
2015 — conf
Synthesis and verification of cyclic combinational circuits.
SoCC
Jui-Hung Chen, Yung-Chih Chen, Wan-Chen Weng, Ching-Yi Huang, Chun-Yao Wang
2015 J jnl
Synthesis for Width Minimization in the Single-Electron Transistor Array.
IEEE Trans. Very Large Scale Integr. Syst.
Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan
2015 A conf
Using structural relations for checking combinationality of cyclic circuits.
DATE
Wan-Chen Weng, Yung-Chih Chen, Jui-Hung Chen, Ching-Yi Huang, Chun-Yao Wang
2014 B conf
Alzheimer's disease classification based on gait information.
IJCNN
Wei-Hsin Wang, Yu-Liang Hsu, Ming-Chyi Pai, Cheng-Hsiung Wang, Chun-Yao Wang, Chien-Wen Lin, Hao-Li Wu, Pau-Choo Chung
2014 A conf
BDD-based synthesis of reconfigurable single-electron transistor arrays.
ICCAD
Zheng Zhao, Chian-Wei Liu, Chun-Yao Wang, Weikang Qian
2014 J jnl
Gait and Balance Analysis for Patients With Alzheimer's Disease Using an Inertial-Sensor-Based Wearable Instrument.
IEEE J. Biomed. Health Informatics
Yu-Liang Hsu, Pau-Choo Chung, Wei-Hsin Wang, Ming-Chyi Pai, Chun-Yao Wang, Chien-Wen Lin, Hao-Li Wu, Jeen-Shing Wang
2014 A conf
Rewiring for threshold logic circuit minimization.
DATE
Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang
2014 A conf
Width minimization in the Single-Electron Transistor array synthesis.
DATE
Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
2013 J jnl
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays.
ACM J. Emerg. Technol. Comput. Syst.
Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan
2013 A conf
On reconfigurable single-electron transistor arrays synthesis using reordering techniques.
DATE
Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
2013 C conf
Pattern generation for Mutation Analysis using Genetic Algorithms.
ISCAS
Yen-Chi Yang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen
2013 A conf
Sensitization criterion for threshold logic circuits and its application.
ICCAD
Chen-Kuan Tsai, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen
2013 J jnl
Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang
2012 A conf
A probabilistic analysis method for functional qualification under Mutation Analysis.
DATE
Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen
2012 — conf
CA-ABAC: Class Algebra Attribute-Based Access Control.
Web Intelligence/IAT Workshops
Daniel J. Buehrer, Chun-Yao Wang
2012 J jnl
Deco: A Decentralized, Cooperative Atomic Commit Protocol.
J. Comput. Networks Commun.
Daniel J. Buehrer, Chun-Yao Wang
2012 — conf
Error Injection & Correction: An efficient formal logic restructuring algorithm.
ISOCC
Ching-Yi Huang, Daw-Ming Lee, Chun-Chi Lin, Chun-Yao Wang
2012 C conf
Gait analysis for patients with Alzheimer'S disease using a triaxial accelerometer.
ISCAS
Pau-Choo Chung, Yu-Liang Hsu, Chun-Yao Wang, Chien-Wen Lin, Jeen-Shing Wang, Ming-Chyi Pai
2012 J jnl
Logic Restructuring Using Node Addition and Removal.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yung-Chih Chen, Chun-Yao Wang
2011 — conf
A register-transfer level testability analyzer.
SoCC
Yen-An Chen, Chun-Yao Wang, Ching-Yi Huang, Hsiu-Yi Lin
2011 A* conf
Automated mapping for reconfigurable single-electron transistor arrays.
DAC
Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan
2011 A conf
On rewiring and simplification for canonicity in threshold logic circuits.
ICCAD
Pin-Yi Kuo, Chun-Yao Wang, Ching-Yi Huang
2010 C conf
Distributed Transactions for Semantic Web Workflows - Overcoming the CAP Limitations on Virtual Organizations.
ISPA
Daniel J. Buehrer, Chun-Yao Wang
2010 J jnl
Fast Node Merging With Don't Cares Using Logic Implications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yung-Chih Chen, Chun-Yao Wang
2010 A* conf
Node addition and removal in the presence of don't cares.
DAC
Yung-Chih Chen, Chun-Yao Wang
2010 C conf
The Cadabia Cloud.
ISPA
Daniel J. Buehrer, Chun-Yao Wang, Li-Ren Chien
2009 — conf
A novel ACO-based pattern generation for peak power estimation in VLSI circuits.
ISQED
Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsin Chang
2009 — conf
An efficient approach to sip design integration.
ISQED
Meng-Syue Chan, Chun-Yao Wang, Yung-Chih Chen
2009 — conf
Dependent latch identification in the reachable state space.
ASP-DAC
Chen-Hsuan Lin, Chun-Yao Wang
2009 J jnl
Dependent-Latch Identification in Reachable State Space.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chen-Hsuan Lin, Chun-Yao Wang, Yung-Chih Chen
2009 — conf
Enhancing SAT-based sequential depth computation by pruning search space.
ACM Great Lakes Symposium on VLSI
Yung-Chih Chen, Chun-Yao Wang
2009 A conf
Fast detection of node mergers using logic implications.
ICCAD
Yung-Chih Chen, Chun-Yao Wang
2009 A conf
Rewiring using IRredundancy Removal and Addition.
DATE
Chun-Chi Lin, Chun-Yao Wang
2008 — conf
A Ring-Based Decentralized Collaborative Non-blocking Atomic Commit Protocol.
IAT
Chun-Yao Wang, Daniel J. Buehrer
2008 — conf
A Statistic-Based Approach to Testability Analysis.
ISQED
Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen
2008 J jnl
An Implicit Approach to Minimizing Range-Equivalent Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yung-Chih Chen, Chun-Yao Wang
2008 J jnl
Novel Probabilistic Combinational Equivalence Checking.
IEEE Trans. Very Large Scale Integr. Syst.
Shih-Chieh Wu, Chun-Yao Wang, Yung-Chih Chen
2008 J jnl
Synthesis of reversible sequential elements.
ACM J. Emerg. Technol. Comput. Syst.
Min-Lun Chuang, Chun-Yao Wang
2008 J jnl
Verification of Pin-Accurate Port Connections.
IEEE Des. Test Comput.
Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou
2007 J jnl
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang
2007 — conf
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure.
ISQED
Yu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, Pei-Hsin Ho
2007 — conf
Recognition of Fanout-free Functions.
ASP-DAC
Tsung-Lin Lee, Chun-Yao Wang
2007 — conf
Synthesis of Reversible Sequential Elements.
ASP-DAC
Min-Lun Chuang, Chun-Yao Wang
2006 — conf
High level equivalence symmetric input identification.
ASP-DAC
Ming-Hong Su, Chun-Yao Wang
2006 — conf
Language-Based High Level Transaction Extraction on On-chip Buses.
ISQED
Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen
2006 C conf
PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking.
VLSI-SoC
Shih-Chieh Wu, Chun-Yao Wang
2006 — conf
The Potential and Limitation of Probability-Based Combinational Equivalence Checking.
ATS
Shih-Chieh Wu, Chun-Yao Wang, Jan-an Hsieh
2005 C conf
An Improved Approach for AlternativeWires Identi.cation.
ICCD
Yung-Chih Chen, Chun-Yao Wang
2004 C conf
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs.
ICCD
Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou
2004 — conf
Using a Class Algebra Ontology To Define Conversions between OWL/SQL/Java Beans.
Web Intelligence
Daniel J. Buehrer, Chun-Yao Wang
2004 A conf
Verification on Port Connections.
ITC
Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang
2003 — conf
An automatic interconnection rectification technique for SoC design integration.
ASP-DAC
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2003 J jnl
Automatic interconnection rectification for SoC design verification based on the port order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2003 — conf
SoC design integration by using automatic interconnection rectification.
ISCAS (4)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2002 J jnl
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2002 J jnl
On automatic-verification pattern generation for SoC withport-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2001 — conf
An AVPG for SOC design verification with port order fault model.
ISCAS (5)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2001 — conf
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model.
Asian Test Symposium
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2001 — conf
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model.
HLDVT
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou