Chun-Po Huang

15 papers A* 2C 4Journal 6Unranked 3
YearRankTypeTitle / Venue / Authors
2018 — conf
A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process.
VLSI-DAT
Wen-Chia Luo, Soon-Jyh Chang, Chun-Po Huang, Hao-Sheng Wu
2018 J jnl
A 12-b 40-MS/s Calibration-Free SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chung-Wei Hsu, Soon-Jyh Chang, Chun-Po Huang, Li-Jen Chang, Ya-Ting Shyu, Chih-Huei Hou, Hwa-An Tseng, Chih-Yuan Kung, Huan-Jui Hu
2018 C conf
A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window.
ISCAS
Chih-Yuan Kung, Chun-Po Huang, Chia-Chuan Li, Soon-Jyh Chang
2017 C conf
A 12-bit 40-MS/s calibration-free SAR ADC.
ISCAS
Chung-Wei Hsu, Li-Jen Chang, Chun-Po Huang, Soon-Jyh Chang
2016 J jnl
A Systematic Design Methodology of Asynchronous SAR ADCs.
IEEE Trans. Very Large Scale Integr. Syst.
Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, Soon-Jyh Chang
2016 C conf
A pipeline ADC with latched-based ring amplifiers.
ISCAS
Wen-Tze Chen, Ya-Ting Shyu, Chun-Po Huang, Soon-Jyh Chang
2016 J jnl
An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang
2016 J jnl
Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs.
IEEE Trans. Instrum. Meas.
Chun-Po Huang, Hsin-Wen Ting, Soon-Jyh Chang
2015 — conf
A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer.
VLSI-DAT
Tien-Feng Hsu, Chun-Po Huang, I-Jen Chao, Soon-Jyh Chang
2014 — conf
Low power pipelined SAR ADC with loading-free architecture.
VLSI-DAT
Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, Guan-Ying Huang
2013 J jnl
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst.
Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang
2012 C conf
A power-efficient sizing methodology of SAR ADCs.
ISCAS
Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang, Cheng-Wu Lin
2012 J jnl
Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang
2011 A* conf
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits.
DAC
Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang
2010 A* conf
Performance-driven analog placement considering boundary constraint.
DAC
Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang