Chun-Hua Cheng

29 papers A* 2A 1C 2Misc 1Journal 13Unranked 10
YearRankTypeTitle / Venue / Authors
2020 Misc conf
Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers.
VTS
Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng
2016 J jnl
Power-mode-aware buffer synthesis for low-power clock skew minimization.
IEICE Electron. Express
Shih-Hsu Huang, Chun-Hua Cheng
2014 — conf
Live demonstration: A low-power high-level synthesis system.
APCCAS
Hua-Hsin Yeh, Chun-Hua Cheng, Shih-Hsu Huang
2013 A conf
Co-synthesis of data paths and clock control paths for minimum-period clock gating.
DATE
Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng
2012 C conf
A formal approach to slack-driven high-level synthesis.
ISCAS
Hua-Hsin Yeh, Shih-Hsu Huang, Chun-Hua Cheng
2012 — conf
Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits.
ASP-DAC
Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng
2012 — conf
Simultaneous wafer bonding type selection and layer assignment for TSV count minimization.
APCCAS
Chun-Hua Cheng, Wei-Shuo Tzeng, Shih-Hsu Huang
2011 J jnl
Accurate TSV Number Minimization in High-Level Synthesis.
J. Inf. Sci. Eng.
Chih-Hung Lee, Shih-Hsu Huang, Chun-Hua Cheng
2011 — conf
Teaching three-dimensional system-in-package design automation in a semester course.
MSE
Shih-Hsu Huang, Wen-Pin Tu, Hua-Hsin Yeh, Chun-Hua Cheng
2010 J jnl
Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization.
J. Inf. Sci. Eng.
Shih-Hsu Huang, Chun-Hua Cheng
2009 J jnl
An ILP approach to surge current minimization in high-level synthesis.
IEICE Electron. Express
Shih-Hsu Huang, Jheng-Fu Yeh, Chun-Hua Cheng
2009 J jnl
Minimum-Period Register Binding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shih-Hsu Huang, Chun-Hua Cheng
2009 J jnl
Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization.
J. Inf. Sci. Eng.
Shih-Hsu Huang, Chun-Hua Cheng, Da-Chen Tzeng
2009 C conf
Surge Current Minimization in High-level Synthesis.
ISCAS
Jheng-Fu Yeh, Chun-Hua Cheng, Shih-Hsu Huang
2009 J jnl
Synthesis of Anti-Aging Gated Clock Designs.
J. Inf. Sci. Eng.
Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan
2009 — conf
Timing driven power gating in high-level synthesis.
ASP-DAC
Shih-Hsu Huang, Chun-Hua Cheng
2008 J jnl
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shih-Hsu Huang, Chun-Hua Cheng
2008 J jnl
Module binding for low power clock gating.
IEICE Electron. Express
Chun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu
2008 J jnl
Power-Management Scheduling for Peak Power Minimization.
J. Inf. Sci. Eng.
Shih-Hsu Huang, Chun-Hua Cheng
2007 A* conf
Clock Period Minimization with Minimum Delay Insertion.
DAC
Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh
2007 J jnl
Operation scheduling for the synthesis of false loop free circuits.
IEICE Electron. Express
Shih-Hsu Huang, Chun-Hua Cheng
2007 — conf
Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential.
EUC Workshops
Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng
2006 — conf
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management.
JCIS
Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang
2006 J jnl
An ILP Approach to the Slack Driven Scheduling Problem.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shih-Hsu Huang, Chun-Hua Cheng
2006 — conf
Operation Scheduling for False Loop Free Circuits.
APCCAS
Shih-Hsu Huang, Chun-Hua Cheng
2006 — conf
Peak Power Minimization through Power Management Scheduling.
APCCAS
Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang
2006 A* conf
Register binding for clock period minimization.
DAC
Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu
2005 — conf
A formal approach to the slack driven scheduling problem in high-level synthesis.
ISCAS (6)
Shih-Hsu Huang, Chun-Hua Cheng
2005 J jnl
Three-dimension scheduling under multi-cycle interconnect communications.
IEICE Electron. Express
Shih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng