Chun-Chuan Chi

12 papers A* 1A 1B 2Misc 1Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2014 J jnl
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base.
IEEE Trans. Very Large Scale Integr. Syst.
Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2014 J jnl
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs.
IEEE Des. Test
Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng
2013 Misc conf
3D-IC interconnect test, diagnosis, and repair.
VTS
Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin
2012 — conf
3D-IC BISR for stacked memories using cross-die spares.
VLSI-DAT
Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin
2012 J jnl
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper.
J. Electron. Test.
Erik Jan Marinissen, Chun-Chuan Chi, Mario Konijnenburg, Jouke Verbree
2011 A* conf
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.
DAC
Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang
2011 B conf
DfT Architecture for 3D-SICs with Multiple Towers.
ETS
Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2011 — conf
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base.
Asian Test Symposium
Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2011 A conf
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base.
ITC
Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2010 — conf
3D DfT architecture for pre-bond and post-bond testing.
3DIC
Erik Jan Marinissen, Chun-Chuan Chi, Jouke Verbree, Mario Konijnenburg
2010 B conf
A low-cost and scalable test architecture for multi-core chips.
ETS
Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li
2009 — conf
Test Integration for SOC Supporting Very Low-Cost Testers.
Asian Test Symposium
Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu