Chun-Cheng Liu

25 papers Misc 2Journal 12Unranked 11
YearRankTypeTitle / Venue / Authors
2025 J jnl
Discovering Key Successful Factors of Mobile Advertisements Using Feature Selection Approaches.
Big Data Cogn. Comput.
Kai-Fu Yang, Venkateswarlu Nalluri, Chun-Cheng Liu, Long-Sheng Chen
2021 J jnl
Enhanced Over-Representation Analysis for the Differential Regulation of Birc5a and HIF2α-Knockdown Approaches.
J. Comput. Biol.
Chun-Cheng Liu, Tao-Chuan Shih, Tun-Wen Pai, Chin-Hwa Hu, Wen-Shyong Tzou
2020 — conf
6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology.
ISSCC
Tamer A. Ali, Ehung Chen, Henry Park, Ramy Yousry, Yu-Ming Ying, Mohammed Abdullatif, Miguel Gandara, Chun-Cheng Liu, Po-Shuan Weng, Huan-Sheng Chen, Mohammad Elbadry, Qaiser Nehal, Kun-Hung Tsai, Kevin Tan, Yi-Chieh Huang, Chung-Hsien Tsai, Yuyun Chang, Yuan-Hao Tung
2020 — conf
Enhanced Functional Pathway Annotations for Differentially Expressed Gene Clusters.
ISBRA
Chun-Cheng Liu, Tao-Chuan Shih, Tun-Wen Pai, Chin-Hwa Hu, Lee-Jyi Wang
2019 — conf
A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology.
ISSCC
Tamer A. Ali, Ramy Yousry, Henry Park, Ehung Chen, Po-Shuan Weng, Yi-Chieh Huang, Chun-Cheng Liu, Chien-Hua Wu, Shih-Hao Huang, Chungshi Lin, Ke-Chung Wu, Kun-Hung Tsai, Kai-Wen Tan, Ahmed ElShater, Kuang-Ren Chen, Wei-Hao Tsai, Huan-Sheng Chen, Weiyu Leng, Mazen Soliman
2017 — conf
28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter.
ISSCC
Chun-Cheng Liu, Mu-Chen Huang
2016 — conf
27.4 A 0.35mW 12b 100MS/s SAR-assisted digital slope ADC in 28nm CMOS.
ISSCC
Chun-Cheng Liu
2016 J jnl
A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC.
IEEE J. Solid State Circuits
Chun-Cheng Liu, Mu-Chen Huang, Yu-Hsuan Tu
2016 Misc conf
Biological Pathway Analysis for De Novo Transcriptomes through Multiple Reference Species Selections.
CISIS
Chun-Cheng Liu, Chien-Ming Chen, Cin-Han Yang, Tun-Wen Pai, Phaik-Eem Lim, Siew-Moi Phang, Sze-Wan Poong, Kok-Keong Lee
2015 J jnl
A 0.022 mm
IEEE J. Solid State Circuits
Tze-Chien Wang, Yu-Hsin Lin, Chun-Cheng Liu
2015 J jnl
A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS.
IEEE J. Solid State Circuits
Chun-Cheng Liu, Che-Hsun Kuo, Ying-Zu Lin
2015 Misc conf
Exclusive Genomic Pathway Analysis for Groupers Infected by Different Iridovirus.
CISIS
Chun-Cheng Liu, Chien-Ming Chen, Tun-Wen Pai, Hsin-Yiu Chou, Hui-Huang Hsu
2014 — conf
A 0.022mm
A-SSCC
Tze-Chien Wang, Yu-Hsin Lin, Chun-Cheng Liu
2014 — conf
A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS.
A-SSCC
Chun-Cheng Liu
2013 J jnl
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method.
IEEE Trans. Very Large Scale Integr. Syst.
Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin
2013 J jnl
A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu, Yen-Ting Liu, Soon-Jyh Chang
2013 J jnl
Optimal Sensor Placement for Stay Cable Damage Identification of Cable-Stayed Bridge under Uncertainty.
Int. J. Distributed Sens. Networks
Li-Qun Hou, Xue-Feng Zhao, Rui-Cong Han, Chun-Cheng Liu
2012 J jnl
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications.
IEEE J. Solid State Circuits
Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin
2011 — conf
A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS.
A-SSCC
Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu, Guan-Ying Huang, Chun-Cheng Liu
2011 — conf
Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation.
ASP-DAC
Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang
2010 J jnl
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure.
IEEE J. Solid State Circuits
Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin
2010 J jnl
A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Jin-Fu Lin, Soon-Jyh Chang, Chun-Cheng Liu, Chih-Hao Huang
2010 — conf
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation.
ISSCC
Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, Chih-Hao Huang, Linkai Bu, Chih-Chung Tsai
2010 J jnl
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang
2009 — conf
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS.
ISSCC
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang