Chulwoo Kim - RankMe

211 papers C 10Misc 2Journal 130Unranked 67

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 15-Gb/s PAM-3 Transceiver With Hybrid Equalization and Time-Domain Decoder for High-Bandwidth-Memory Interfaces. IEEE J. Solid State Circuits Hwaseok Shin, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Junseob So, Seon-Been Lee, Taehwan Kim, Chulwoo Kim
2026	J	`jnl`	A 20-Gb/s/pin 0.42-pJ/b Single-Ended Receiver With Ping-Pong Self-Referencing Technique. IEEE Trans. Circuits Syst. II Express Briefs Seongcheol Kim, Changmin Sim, Seungwoo Park, Junseob So, Hwaseok Shin, Taewhan Kim, Seon-Been Lee, Chulwoo Kim
2026	J	`jnl`	A 7-bit 1.15-GS/s 2.6-bit/Cycle Asynchronous SAR ADC Using Comparator Decision Skip Technique With Background Offset Calibration. IEEE J. Solid State Circuits Sooho Park, Changjoo Kim, Yohan Choi, Minkyun Shim, Woojin Lee, Donghwi Seo, Chulwoo Kim
2025	—	`conf`	22.5 A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer. ISSCC Junseob So, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Hwaseok Shin, Seonbeen Lee, Taehwan Kim, Chulwoo Kim
2025	J	`jnl`	A 10 Gb/s Single-Ended Receiver Using Time Gap Sense Amplifier for Next-Generation HBM. IEEE Trans. Circuits Syst. II Express Briefs Taehwan Kim, Changmin Sim, Seungwoo Park, Jinwoo Park, Seongcheol Kim, Hwaseok Shin, Junseob So, Seonbeen Lee, Youngwook Kwon, Chulwoo Kim
2025	J	`jnl`	A 28-Gb/s Single-Ended PAM-4 Transceiver With Active-Inductor Equalizer and Amplitude- Detection LSB Decoder for Memory Interfaces. IEEE Trans. Very Large Scale Integr. Syst. Hwaseok Shin, Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Junseob So, Taehwan Kim, Chulwoo Kim
2025	J	`jnl`	A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation. IEEE Solid State Circuits Lett. Woojin Lee, Changmin Sim, Changjoo Kim, Jinwoo Jeon, Hyundo Jung, Taihyun Kim, Chulwoo Kim
2025	J	`jnl`	A 50 Gb/s PAM-4 Transceiver With High-Swing Driver, Dual-Loop Analog Equalizer, and Integrator-Based Baud-Rate Linear CDR for Short-Reach Links. IEEE Trans. Circuits Syst. I Regul. Pap. Jincheol Sim, Changmin Sim, Jonghyuck Choi, Seungwoo Park, Seongcheol Kim, Chulwoo Kim
2025	J	`jnl`	A 52-Gb/s Low-Power PAM-4 Baud-Rate CDR Using Pattern-Based Phase Detector for Short-Reach Applications. IEEE J. Solid State Circuits Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Changmin Sim, Seongcheol Kim, Chulwoo Kim
2025	J	`jnl`	An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration. IEEE Solid State Circuits Lett. Changjoo Kim, Sooho Park, Yohan Choi, Minkyun Shim, Woojin Lee, Donghwi Seo, Chulwoo Kim
2025	J	`jnl`	Erratum to "A 7-bit 1.15-GS/s 2.6-bit/Cycle Asynchronous SAR ADC Using Comparator Decision Skip Technique With Background Offset Calibration". IEEE J. Solid State Circuits Sooho Park, Changjoo Kim, Yohan Choi, Minkyun Shim, Woojin Lee, Donghwi Seo, Chulwoo Kim
2025	—	`conf`	Rethinking Heuristics, Are We Heading the Right Way? A Case Study on Heuristic Evaluation in Action. CHI Extended Abstracts May Jorella S. Lazaro, Chulwoo Kim, Ji Soo Yi
2024	J	`jnl`	A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling. IEEE Trans. Circuits Syst. II Express Briefs Seungwoo Park, Yoonjae Choi, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Changmin Sim, Seongcheol Kim, Chulwoo Kim
2024	J	`jnl`	A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces. IEEE J. Solid State Circuits Seongcheol Kim, Changmin Sim, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Junseob So, Hwaseok Shin, Seonbeen Lee, Chulwoo Kim
2024	J	`jnl`	A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances. IEEE J. Solid State Circuits Jincheol Sim, Changmin Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Jong-Min Kim, Ju-Hyung Lee, Young-Chai Ko, Chulwoo Kim
2024	J	`jnl`	A 101.6-dB-SNDR Fully Dynamic Zoom ADC Using Miller-Compensated Floating Inverter Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs Yohan Choi, Woojin Lee, Sooho Park, Changjoo Kim, Hyundo Jung, Chulwoo Kim
2024	J	`jnl`	A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
2024	J	`jnl`	A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. Yoonjae Choi, Changmin Sim, Jonghyuck Choi, Jincheol Sim, Hyunsu Park, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Chulwoo Kim
2024	J	`jnl`	A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications. IEEE J. Solid State Circuits HyunJin Kim, ChangHun Park, Inho Park, Taehyeong Park, Seungwoo Park, Chulwoo Kim
2024	J	`jnl`	A Fully Integrated Dual-Output Continuously Scalable-Conversion-Ratio SC Converter for Battery-Powered IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Taehyeong Park, HyunJin Kim, Mingi Jeong, Inho Park, Chulwoo Kim
2024	J	`jnl`	A Fully Integrated Nine-Ratio Switched-Capacitor Converter With Overlapped-Conversion-Ratio Modulation for IoT Applications. IEEE J. Solid State Circuits HyunJin Kim, Taehyeong Park, Inho Park, ChangHun Park, Seokjin Kim, Seokhee Han, Junwon Jeong, Chulwoo Kim
2024	J	`jnl`	A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces. IEEE J. Solid State Circuits Jonghyuck Choi, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
2024	J	`jnl`	A Time-Based Direct MPPT Technique for Low-Power Photovoltaic Energy Harvesting. IEEE Trans. Ind. Electron. Junyoung Maeng, Junwon Jeong, Inho Park, Minseob Shim, Chulwoo Kim
2024	J	`jnl`	A Tri-Mode Reconfigurable DC-DC Converter With Photovoltaic Energy Harvesting for Miniature IoT Batteries. IEEE Trans. Circuits Syst. II Express Briefs Junyoung Maeng, Inho Park, Jinwoo Jeon, HyunJin Kim, Hoi Lee, Chulwoo Kim
2024	J	`jnl`	A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques. IEEE J. Solid State Circuits Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Hwaseok Shin, Junseob So, Seonbeen Lee, Chulwoo Kim
2024	J	`jnl`	Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces. IEEE J. Solid State Circuits Seongcheol Kim, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Changmin Sim, Junseob So, Taehyeong Park, Chulwoo Kim
2023	—	`conf`	A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications. ISSCC Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Chulwoo Kim
2023	J	`jnl`	A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces. IEEE Trans. Circuits Syst. II Express Briefs Seongcheol Kim, Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim
2023	J	`jnl`	A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE. IEEE Trans. Circuits Syst. II Express Briefs Jonghyuck Choi, Yoonjae Choi, Hyunsu Park, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Chulwoo Kim
2023	J	`jnl`	A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces. IEEE J. Solid State Circuits Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
2023	J	`jnl`	A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces. IEEE J. Solid State Circuits Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Kyeong-Min Kim, Changkyu Choi, Hae-Kang Jung, Chulwoo Kim
2023	J	`jnl`	A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Changmin Sim, Chulwoo Kim
2023	J	`jnl`	A Thermoelectric Energy-Harvesting Interface With Dual-Conversion Reconfigurable DC-DC Converter and Instantaneous Linear Extrapolation MPPT Method. IEEE J. Solid State Circuits Inho Park, Jinwoo Jeon, HyunJin Kim, Taehyeong Park, Junwon Jeong, Chulwoo Kim
2023	J	`jnl`	PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance. IEEE Trans. Circuits Syst. I Regul. Pap. Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim
2022	—	`conf`	A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces. ISSCC Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim
2022	J	`jnl`	A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Chulwoo Kim
2022	J	`jnl`	A 2.4-8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input-Output Phase Detection. IEEE Trans. Circuits Syst. II Express Briefs Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim
2022	J	`jnl`	A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End. IEEE Trans. Circuits Syst. II Express Briefs Jincheol Sim, Yeonho Lee, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim
2022	C	`conf`	A 266-3750 MHz Wide-Range Adaptive Phase-Rotator-Based All Digital DLL for LPDDR5 Controllers. ISCAS Jeewan Lee, Yoonjae Choi, Chulwoo Kim
2022	J	`jnl`	A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations. IEEE J. Solid State Circuits Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim
2022	J	`jnl`	A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant Interpolation Technique. IEEE J. Solid State Circuits Jaegeun Song, Yunsoo Park, Chaegang Lim, Yohan Choi, Soonsung Ahn, Sooho Park, Chulwoo Kim
2022	—	`conf`	A 97.9% Peak Efficiency 9 V Output Three-Switch Hybrid Buck-Boost Power Stage Using 5 V CMOS. MWSCAS HyunJin Kim, Taehyeong Park, Chulwoo Kim
2022	J	`jnl`	An 88.9-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter. IEEE J. Solid State Circuits Chaegang Lim, Yohan Choi, Jaegeun Song, Soonsung Ahn, Seokwon Jang, Chulwoo Kim
2022	—	`conf`	An Output-Boosted 3-ratio Switched-Capacitor DC-DC Converter with 0.5-to-1.8 V Output Voltage Range for Low-Power IoT Applications. MWSCAS HyunJin Kim, ChangHun Park, Chulwoo Kim
2022	J	`jnl`	Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Jonghyuck Choi, Yoonjae Choi, Hyunsu Park, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Chulwoo Kim
2022	—	`conf`	Experimental Demonstration of RoFSO Transmission Combining WLAN Standard and WDM-FSO over 100m Distance. INFOCOM Workshops Jong-Min Kim, Ju-Hyung Lee, Yeongrok Lee, Hong-Seol Cha, Hyunsu Park, Jincheol Sim, Chulwoo Kim, Young-Chai Ko
2021	J	`jnl`	30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links. IEEE J. Solid State Circuits Hyunsu Park, Junyoung Song, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Jeongsik Yoo, Chulwoo Kim
2021	J	`jnl`	A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Yoonjae Choi, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Chulwoo Kim
2021	C	`conf`	A 1-3.2 GHz 0.6 mW/GHz Duty-Cycle-Corrector Using Bangbang Duty-Cyle-Detector. ISCAS Jincheol Sim, Hyunsu Park, Youngwook Kwon, Seongcheol Kim, Chulwoo Kim
2021	J	`jnl`	A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. IEEE J. Solid State Circuits Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim
2021	J	`jnl`	A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector. IEEE Access Yoonjae Choi, Sewook Hwang, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Chulwoo Kim
2021	J	`jnl`	A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. Junyoung Song, Sewook Hwang, Chulwoo Kim
2021	J	`jnl`	A 90.2% Peak Efficiency Multi-Input Single-Inductor Multi-Output Energy Harvesting Interface With Double-Conversion Rejection Technique and Buck-Based Dual-Conversion Mode. IEEE J. Solid State Circuits HyunJin Kim, Junyoung Maeng, Inho Park, Jinwoo Jeon, Dongju Lim, Chulwoo Kim
2021	J	`jnl`	A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs. IEEE Trans. Circuits Syst. I Regul. Pap. Chaegang Lim, Yohan Choi, Yunsoo Park, Jaegeun Song, Soonsung Ahn, Sooho Park, Chulwoo Kim
2021	J	`jnl`	A Dual-Mode Continuously Scalable-Conversion-Ratio SC Energy Harvesting Interface With SC-Based PFM MPPT and Flying Capacitor Sharing Scheme. IEEE J. Solid State Circuits HyunJin Kim, Junyoung Maeng, Inho Park, Jinwoo Jeon, Yohan Choi, Chulwoo Kim
2021	J	`jnl`	A High-Voltage Dual-Input Buck Converter With Bidirectional Inductor Current for Triboelectric Energy-Harvesting Applications. IEEE J. Solid State Circuits Junyoung Maeng, Inho Park, Minseob Shim, Junwon Jeong, Chulwoo Kim
2021	C	`conf`	A Hybrid DC-DC Converter Capable of Supplying Heavy Load in Step-Up and Step-Down Mode. ISCAS Jinwoo Jeon, Junyoung Maeng, Inho Park, HyunJin Kim, Chulwoo Kim
2021	C	`conf`	A Power Management System Based on Adaptive Low-Dropout Voltage Regulator with Optimal Reference Pre-Compensation Technique. ISCAS Inho Park, Jinseok Oh, Chulwoo Kim
2020	J	`jnl`	A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique. IEEE Trans. Circuits Syst. II Express Briefs Jaegeun Song, Jaehun Jun, Chulwoo Kim
2020	—	`conf`	A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique. ISOCC Soonsung Ahn, Jaegeun Song, Chaegang Lim, Yohan Choi, Sooho Park, Yunsoo Park, Chulwoo Kim
2020	J	`jnl`	A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications. IEEE Trans. Circuits Syst. Youngbog Yoon, Hyunsu Park, Chulwoo Kim
2020	J	`jnl`	A High-Voltage Dual-Input Buck Converter Achieving 52.9% Maximum End-to-End Efficiency for Triboelectric Energy-Harvesting Applications. IEEE J. Solid State Circuits Inho Park, Junyoung Maeng, Minseob Shim, Junwon Jeong, Chulwoo Kim
2020	J	`jnl`	A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays With Fully Integrated 7.2-pF Total Capacitance. IEEE J. Solid State Circuits Junyoung Maeng, Minseob Shim, Junwon Jeong, Inho Park, Yunsoo Park, Chulwoo Kim
2020	J	`jnl`	An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier. IEEE J. Solid State Circuits Yunsoo Park, Jaegeun Song, Yohan Choi, Chaegang Lim, Soonsung Ahn, Chulwoo Kim
2020	J	`jnl`	An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme With the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications. IEEE Trans. Circuits Syst. II Express Briefs Youngbog Yoon, Chulwoo Kim
2020	J	`jnl`	Near threshold voltage digital PLL using low voltage optimised blocks for AR display system. IET Circuits Devices Syst. Jaehun Jun, Sangsu Lee, Chulwoo Kim
2019	J	`jnl`	12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. IEEE J. Solid State Circuits Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang-Geun Bae, Jaehun Jun, Chulwoo Kim
2019	—	`conf`	A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface. ISSCC Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim
2019	J	`jnl`	A 42 nJ/Conversion On-Demand State-of-Charge Indicator for Miniature IoT Li-Ion Batteries. IEEE J. Solid State Circuits Junwon Jeong, Seokhyeon Jeong, Dennis Sylvester, David T. Blaauw, Chulwoo Kim
2019	J	`jnl`	A 9 Gb/s/ch Transceiver With Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs Junyoung Song, Yongtae Kim, Chulwoo Kim
2019	—	`conf`	A Bidirectional High-Voltage Dual-Input Buck Converter for Triboelectric Energy-Harvesting Interface Achieving 70.72% End-to-End Efficiency. VLSI Circuits Inho Park, Junyoung Maeng, Minseob Shim, Junwon Jeong, Chulwoo Kim
2019	J	`jnl`	A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs Sang-Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2018	—	`conf`	12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. ASP-DAC Yeonho Lee, Yoonjae Choi, Chulwoo Kim
2018	J	`jnl`	A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim
2018	J	`jnl`	A 3D anthropometric sizing analysis system based on North American CAESAR 3D scan data for design of head wearable products. Comput. Ind. Eng. Wonsup Lee, Baekhee Lee, Xiaopeng Yang, Hayoung Jung, Ilgeun Bok, Chulwoo Kim, Ochae Kwon, Heecheon You
2018	—	`conf`	A 4.5-to-16μW integrated triboelectric energy-harvesting system based on high-voltage dual-input buck converter with MPPT and 70V maximum input voltage. ISSCC Inho Park, Junyoung Maeng, Dongju Lim, Minseob Shim, Junwon Jeong, Chulwoo Kim
2018	—	`conf`	A 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries. ASP-DAC Junwon Jeong, Seokhyeon Jeong, Chulwoo Kim, Dennis Sylvester, David T. Blaauw
2018	J	`jnl`	A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX. IEEE Trans. Circuits Syst. II Express Briefs Jeongsik Yoo, Yeonho Lee, Yoonjae Choi, Hyunsu Park, Sanghune Park, Chulwoo Kim
2018	J	`jnl`	A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. Jaehun Jun, Jaegeun Song, Chulwoo Kim
2018	J	`jnl`	A Spread Spectrum Clock Generator With Nested Modulation Profile for a High-Resolution Display System. IEEE Trans. Circuits Syst. II Express Briefs Jaehun Jun, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim
2018	—	`conf`	Edge pursuit comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC. ASP-DAC Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Junhua Shen, Chulwoo Kim, Dennis Sylvester, David T. Blaauw, Wanyeong Jung
2017	—	`conf`	29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. ISSCC Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim
2017	J	`jnl`	3-Gb/s High-Speed True Random Number Generator Using Common-Mode Operating Comparator and Sampling Uncertainty of D Flip-Flop. IEEE J. Solid State Circuits Sang-Geun Bae, Yongtae Kim, Yunsoo Park, Chulwoo Kim
2017	J	`jnl`	A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system. IEICE Electron. Express Young-Jae Min, Chan-Hui Jeong, Junil Moon, Youngsun Han, Soo-Won Kim, Chulwoo Kim
2017	J	`jnl`	A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim
2017	J	`jnl`	A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. IEEE Trans. Very Large Scale Integr. Syst. Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim
2017	J	`jnl`	A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM. IEEE Trans. Circuits Syst. II Express Briefs Jungtaek You, Junyoung Song, Chulwoo Kim
2017	J	`jnl`	A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier. IEEE Trans. Circuits Syst. II Express Briefs Jayoung Kim, Junyoung Song, Jungtaek You, Sewook Hwang, Sang-Geun Bae, Chulwoo Kim
2017	J	`jnl`	A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation. IEEE Trans. Circuits Syst. II Express Briefs Sang-Geun Bae, Gyungmin Kim, Chulwoo Kim
2017	—	`conf`	A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations. ISOCC Sangsu Lee, Jaehun Jun, Chulwoo Kim
2017	J	`jnl`	Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC. IEEE J. Solid State Circuits Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Junhua Shen, Chulwoo Kim, Dennis Sylvester, David T. Blaauw, Wanyeong Jung
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017	Misc	`conf`	On ROC Curve Analysis of Artificial Neural Network Classifiers. FLAIRS Chulwoo Kim, Sung-Hyuk Cha, Yoo Jung An, Ned Wilson
2016	—	`conf`	A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE. VLSI Circuits Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim
2016	J	`jnl`	A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels. IEEE Trans. Very Large Scale Integr. Syst. Junyoung Song, Sewook Hwang, Chulwoo Kim
2016	J	`jnl`	A Scalable Bandwidth Mismatch Calibration Technique for Time-Interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Yunsoo Park, Jintae Kim, Chulwoo Kim
2016	—	`conf`	A digital low-dropout(DLDO) regulator with 14dB power supply rejection enhancement. ISOCC Byung Gun Joung, Yangho Seo, Chulwoo Kim
2016	J	`jnl`	An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers. IEEE Trans. Very Large Scale Integr. Syst. Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim
2016	—	`conf`	An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC. VLSI Circuits Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Chulwoo Kim, Dennis Sylvester, David T. Blaauw, Wanyeong Jung
2016	J	`jnl`	Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Edith Beigné, Jinuk Luke Shin, Yusuke Oike, Chulwoo Kim, Jan Genoe
2016	—	`conf`	Session 18 overview: High-bandwidth DRAM. ISSCC Chulwoo Kim, Martin Brox
2015	—	`conf`	17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. ISSCC Junyoung Song, Hyun-Woo Lee, Jayoung Kim, Sewook Hwang, Chulwoo Kim
2015	J	`jnl`	A 0.15 V Input Energy Harvesting Charge Pump With Dynamic Body Biasing and Adaptive Dead-Time for Efficiency Improvement. IEEE J. Solid State Circuits Jungmoon Kim, Philip K. T. Mok, Chulwoo Kim
2015	J	`jnl`	A 100-nW 9.1-ENOB 20-kS/s SAR ADC for Portable Pulse Oximeter. IEEE Trans. Circuits Syst. II Express Briefs Hokyu Lee, Sejin Park, Chaegang Lim, Chulwoo Kim
2015	J	`jnl`	A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter. IEEE Trans. Very Large Scale Integr. Syst. Hokyu Lee, Aurangozeb, Sejin Park, Jintae Kim, Chulwoo Kim
2015	—	`conf`	Circuit design techniques for multimedia wireline communications. ASICON Chulwoo Kim
2015	J	`jnl`	D Microprocess. Microsystems Joon Goo Lee, Seon Wook Kim, Dong-Hyun Kim, Younga Cho, Jae-Sung Rieh, Gyusung Kang, Jongsun Park, Hokyu Lee, Sejin Park, Chulwoo Kim
2015	—	`conf`	F2: Memory trends: From big data to wearable devices. ISSCC Jonathan Chang, Leland Chang, Antoine Dupret, Chulwoo Kim, Fatih Hamzaoglu, Takefumi Yoshikawa
2015	J	`jnl`	Self-Powered 30 µW to 10 mW Piezoelectric Energy Harvesting System With 9.09 ms/V Maximum Power Point Tracking Time. IEEE J. Solid State Circuits Minseob Shim, Jungmoon Kim, Junwon Jeong, Sejin Park, Chulwoo Kim
2014	—	`conf`	23.1 A 0.15V-input energy-harvesting charge pump with switching body biasing and adaptive dead-time for efficiency improvement. ISSCC Jungmoon Kim, Philip K. T. Mok, Chulwoo Kim
2014	—	`conf`	23.7 Self-powered 30μW-to-10mW Piezoelectric energy-harvesting system with 9.09ms/V maximum power point tracking time. ISSCC Minseob Shim, Jungmoon Kim, Junwon Jung, Chulwoo Kim
2014	—	`conf`	25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. ISSCC Hyun-Woo Lee, Junyoung Song, Sangah Hyun, Seunggeun Baek, Yuri Lim, Jungwan Lee, Minsu Park, Haerang Choi, Changkyu Choi, Jin-Youp Cha, Jaeil Kim, Hoon Choi, Seung-Wook Kwack, Yonggu Kang, Jongsam Kim, Junghoon Park, Jonghwan Kim, Jin-Hee Cho, Chulwoo Kim, Yunsaing Kim, Jaejin Lee, Byong-Tae Chung, Sung-Joo Hong
2014	J	`jnl`	A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim
2014	—	`conf`	A DC-DC boost converter with variation tolerant MPPT technique and efficient ZCS circuit for thermoelectric energy harvesting applications. ASP-DAC Jungmoon Kim, Minseob Shim, Junwon Jung, Heejun Kim, Chulwoo Kim
2014	—	`conf`	A digitally controlled DC-DC buck converter with bang-bang control. ICEIC Heejun Kim, Jungmoon Kim, Minseob Shim, Junwon Jung, Sejin Park, Chulwoo Kim
2014	—	`conf`	A single-inductor 8-channel output DC-DC boost converter with time-limited power distribution control and single shared hysteresis comparator. ASP-DAC Jungmoon Kim, Chulwoo Kim
2014	J	`jnl`	An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator. IEEE Trans. Very Large Scale Integr. Syst. Kyeong-Min Kim, Sewook Hwang, Junyoung Song, Chulwoo Kim
2014	—	`conf`	F6: Energy-efficient I/O design for next-generation systems. ISSCC Frank O'Mahony, Nicola Da Dalt, Ken Chang, Hisakatsu Yamaguchi, Chulwoo Kim, Elad Alon
2014	—	`book`	High-Bandwidth Memory Interface Chulwoo Kim, Hyun-Woo Lee, Junyoung Song
2014	J	`jnl`	Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces. IEEE Trans. Very Large Scale Integr. Syst. Hyun-Woo Lee, Chulwoo Kim
2013	J	`jnl`	10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation. IEEE Trans. Very Large Scale Integr. Syst. Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Hojin Park, Chulwoo Kim
2013	J	`jnl`	366-kS/s 1.09-nJ 0.0013-${\rm mm}^{2}$ Frequency-to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase Clock. IEEE Trans. Very Large Scale Integr. Syst. Kisoo Kim, Hokyu Lee, Chulwoo Kim
2013	J	`jnl`	A 0.008 mm IEEE Trans. Circuits Syst. I Regul. Pap. Sewook Hwang, Jabeom Koo, Kisoo Kim, Hokyu Lee, Chulwoo Kim
2013	J	`jnl`	A 1-mW Solar-Energy-Harvesting Circuit Using an Adaptive MPPT With a SAR and a Counter. IEEE Trans. Circuits Syst. II Express Briefs Hoon Ki Kim, Young-Jae Min, Chan-Hui Jeong, Kyu-Young Kim, Chulwoo Kim, Soo-Won Kim
2013	J	`jnl`	A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection. IEEE Trans. Circuits Syst. I Regul. Pap. Junyoung Song, Inhwa Jung, Minyoung Song, Young-Ho Kwak, Sewook Hwang, Chulwoo Kim
2013	J	`jnl`	A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC. IEEE Trans. Circuits Syst. I Regul. Pap. Minyoung Song, Inhwa Jung, Sudhakar Pamarti, Chulwoo Kim
2013	J	`jnl`	A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. Young-Ho Kwak, Yongtae Kim, Sewook Hwang, Chulwoo Kim
2013	J	`jnl`	A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface. IEEE J. Solid State Circuits Soo-Bin Lim, Hyun-Woo Lee, Junyoung Song, Chulwoo Kim
2013	—	`conf`	A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process. ASP-DAC Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Inhwa Jung, Chulwoo Kim
2013	J	`jnl`	A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor. IEEE Trans. Very Large Scale Integr. Syst. Sewook Hwang, Kyeong-Min Kim, Jungmoon Kim, Seon Wook Kim, Chulwoo Kim
2013	J	`jnl`	A Single-Inductor Eight-Channel Output DC-DC Converter With Time-Limited Power Distribution Control and Single Shared Hysteresis Comparator. IEEE Trans. Circuits Syst. I Regul. Pap. Jungmoon Kim, Dong Seok Kim, Chulwoo Kim
2013	—	`conf`	A regulated charge pump with low-power integrated optimum power point tracking algorithm for indoor solar energy harvesting. ASP-DAC Jungmoon Kim, Chulwoo Kim
2013	J	`jnl`	An On-Chip Network Fabric Supporting Coarse-Grained Processor Array. IEEE Trans. Very Large Scale Integr. Syst. Phi-Hung Pham, Phuong Mau, Jungmoon Kim, Chulwoo Kim
2013	—	`conf`	An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. ISSCC Junyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, Chulwoo Kim
2013	J	`jnl`	Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip. IEEE Trans. Very Large Scale Integr. Syst. Phi-Hung Pham, Junyoung Song, Jongsun Park, Chulwoo Kim
2013	J	`jnl`	Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation. IEEE Trans. Very Large Scale Integr. Syst. Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim, Chulwoo Kim
2013	—	`conf`	Robust transceiver based on worst-case SINR optimization for MIMO interfering broadcast channels with imperfect channel knowledge. ICSPCS Hyun-Ho Lee, Young-Chai Ko, Jun Heo, Soo-Won Kim, Chulwoo Kim
2012	J	`jnl`	A 0.31-1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications. IEEE Trans. Very Large Scale Integr. Syst. Young-Jae Min, Chan-Hui Jeong, Kyu-Young Kim, Won Ho Choi, Jong-Pil Son, Chulwoo Kim, Soo-Won Kim
2012	J	`jnl`	A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. IEEE J. Solid State Circuits Hyun-Woo Lee, Hoon Choi, Beom-Ju Shin, Kyung-Hoon Kim, Kyung Whan Kim, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Jae-Hwan Kim, Eun Young Park, Jong-Sam Kim, Jong-Hwan Kim, Jin-Hee Cho, Nam Gyu Rye, Jun Hyun Chun, Yunsaing Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung
2012	J	`jnl`	A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology. IEEE J. Solid State Circuits Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Sohn, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung
2012	—	`conf`	A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. ISSCC Hyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim
2012	J	`jnl`	A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile. IEEE J. Solid State Circuits Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim
2012	J	`jnl`	A 5-Bit 500-MS/S Flash ADC using Time-Domain Comparison. J. Circuits Syst. Comput. Young-Jae Min, Hoon Ki Kim, Chulwoo Kim, Soo-Won Kim, Gil-Su Kim
2012	C	`conf`	A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS. ISCAS Sewook Hwang, Inhwa Jung, Junyoung Song, Chulwoo Kim
2012	—	`conf`	A TDC-based skew compensation technique for high-speed output driver. ISOCC Debashis Dhar, Inhwa Jung, Chulwoo Kim
2012	J	`jnl`	Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. Phi-Hung Pham, Jongsun Park, Phuong Mau, Chulwoo Kim
2012	J	`jnl`	PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration. IEEE Trans. Very Large Scale Integr. Syst. Moo-young Kim, Hokyu Lee, Chulwoo Kim
2011	J	`jnl`	10-bit 100-MS/s Pipelined ADC Using Input-Swapped Opamp Sharing and Self-Calibrated V/I Converter. IEEE Trans. Very Large Scale Integr. Syst. Moo-young Kim, Jinwoo Kim, Tagjong Lee, Chulwoo Kim
2011	J	`jnl`	250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. IEEE J. Solid State Circuits Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong
2011	—	`conf`	A 0.076mm ISSCC Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim
2011	—	`conf`	A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. ISSCC Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Shon, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung
2011	J	`jnl`	A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 µs Frequency Acquisition Time. IEEE Trans. Very Large Scale Integr. Syst. Inhwa Jung, Daejung Shin, Taejin Kim, Chulwoo Kim
2011	J	`jnl`	A Regulated Charge Pump With a Low-Power Integrated Optimum Power Point Tracking Algorithm for Indoor Solar Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs Jungmoon Kim, Jihwan Kim, Chulwoo Kim
2010	C	`conf`	A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. ISCAS Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih
2010	J	`jnl`	A Gb/s+ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time. IEEE Trans. Circuits Syst. II Express Briefs Young-Ho Kwak, Inhwa Jung, Chulwoo Kim
2010	J	`jnl`	A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System. IEEE Trans. Very Large Scale Integr. Syst. Youngsun Han, Peter Harliman, Seon Wook Kim, Jong-Kook Kim, Chulwoo Kim
2010	J	`jnl`	An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling. IEEE Trans. Very Large Scale Integr. Syst. Sunghwa Ok, Kyunghoon Chung, Jabeom Koo, Chulwoo Kim
2010	—	`conf`	An on-chip soft-start technique of current-mode DC-DC converter for biomedical applications. APCCAS Dong Seok Kim, Jungmoon Kim, Jihwan Kim, Chulwoo Kim
2010	J	`jnl`	ProMINoC: An efficient Network-on-Chip design for flexible data permutation. IEICE Electron. Express Phi-Hung Pham, Jongsun Park, Chulwoo Kim
2009	—	`conf`	A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. CICC Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Wooseok Kim, Byeongha Park, Chulwoo Kim
2009	J	`jnl`	A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays. IEEE Trans. Circuits Syst. II Express Briefs Inhwa Jung, Daejung Shin, Taejin Kim, Chulwoo Kim
2009	—	`conf`	A 366kS/s 400uW 0.0013mm CICC Kisoo Kim, Hokyu Lee, Sangdon Jung, Chulwoo Kim
2009	—	`conf`	A 64-PE folded-torus intra-chip communication fabric for guaranteed throughput in Network-on-Chip based applications. CICC Phi-Hung Pham, Phuong Mau, Chulwoo Kim
2009	J	`jnl`	A 7 ps Jitter 0.053 mm IEEE J. Solid State Circuits Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Chulwoo Kim
2009	C	`conf`	A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter. ISCAS Dongsuk Shin, Jabeom Koo, Won-Joo Yun, Young-Jung Choi, Chulwoo Kim
2009	J	`jnl`	A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time. IEEE Trans. Very Large Scale Integr. Syst. Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Chulwoo Kim
2009	J	`jnl`	A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock. IEEE Trans. Circuits Syst. II Express Briefs Jabeom Koo, Sunghwa Ok, Chulwoo Kim
2009	—	`conf`	Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application. CICC Jabeom Koo, Gil-Su Kim, Junyoung Song, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim
2008	J	`jnl`	A 0.004-mm IEEE Trans. Circuits Syst. II Express Briefs Inhwa Jung, Gunok Jung, Janghoon Song, Moo-young Kim, Junyoung Park, Sung-Bae Park, Chulwoo Kim
2008	—	`conf`	A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme. ESSCIRC Dongsuk Shin, Won-Joo Yun, Hyun-Woo Lee, Young-Jung Choi, Suki Kim, Chulwoo Kim
2008	—	`conf`	A 1.2GHz delayed clock generator for high-speed microprocessors. ASP-DAC Inhwa Jung, Moo-young Kim, Chulwoo Kim
2008	—	`conf`	A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation. CICC Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim, Chulwoo Kim
2008	—	`conf`	A 110 dB, 3-mW fourth-order Σ-Δ modulator for atmospheric pressure sensor. SoC Taeyoon Kim, Wonki Park, Heesun Ahn, Kyongwon Min, Sangyong Lee, Jongchan Choi, Chulwoo Kim, Kynnyun Kim, Sungchul Lee
2008	—	`conf`	A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor. CICC Sunghwa Ok, Jungmoon Kim, Gilwon Yoon, Hyunho Chu, Jaegeun Oh, Seon Wook Kim, Chulwoo Kim
2008	J	`jnl`	A monolithic voltage-mode DC-DC converter with a novel oscillator and ramp generator. IEICE Electron. Express Hyunho Chu, Jungmoon Kim, Chulwoo Kim
2008	—	`conf`	A slew-rate controlled output driver with one-cycle tuning time. ASP-DAC Young-Ho Kwak, Inhwa Jung, Chulwoo Kim
2008	J	`jnl`	Wide frequency range duty cycle correction circuit for DDR interface. IEICE Electron. Express Dongsuk Shin, Soo-Won Kim, Chulwoo Kim
2007	—	`conf`	A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC. ISSCC Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim
2007	—	`conf`	A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time. CICC Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Sunghwa Ok, Chulwoo Kim
2007	—	`conf`	A One-Cycle Lock Time Slew-Rate-Controlled Output Driver. ISSCC Young-Ho Kwak, Inhwa Jung, Hyung-Dong Lee, Young-Jung Choi, Yogendera Kumar, Chulwoo Kim
2007	—	`conf`	A wide-range duty-independent all-digital multiphase clock generator. ESSCIRC Hyunsoo Chae, Sangdon Jung, Chulwoo Kim
2007	J	`jnl`	An automatic threshold-converged CMOS optical receiver for high-definition digital audio interfaces. IEICE Electron. Express Gil-Su Kim, Chulwoo Kim, Soo-Won Kim
2007	—	`conf`	Decision Theoretic Perspective on Optimizing Intelligent Help. HCI (3) Chulwoo Kim, Mark R. Lehto
2007	—	`conf`	Effect of Providing a Web-Based Collaboration Medium for Remote Customer Troubleshooting Tasks. HCI (9) Chulwoo Kim, Pilsung Choe, Mark R. Lehto, Jan P. Allebach
2007	—	`conf`	Experimental Comparison of Adaptive vs. Static Thumbnail Displays. HCI (2) Pilsung Choe, Chulwoo Kim, Mark R. Lehto, Jan P. Allebach
2007	J	`jnl`	Noise-Aware Split-Path Domino Logic and its Clock Delaying Scheme. J. Circuits Syst. Comput. Dongkyu Park, Seoksoo Yoon, Inhwa Jung, Chulwoo Kim
2007	J	`jnl`	Sptpl: a New Pulsed Latch Type Flip-Flop in High-Performance System-on-a-Chip (SOC). J. Circuits Syst. Comput. Inhwa Jung, Moo-young Kim, Chulwoo Kim
2006	J	`jnl`	A 120-MHz-1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling. IEEE J. Solid State Circuits Jin-Han Kim, Young-Ho Kwak, Moo-young Kim, Soo-Won Kim, Chulwoo Kim
2006	—	`conf`	A Compact and High Performance Switch for Circuit-Switched Network-On-Chip. SoCC Phi-Hung Pham, Yogendera Kumar, Chulwoo Kim
2006	J	`jnl`	A New Energy x Delay-Aware Flip-Flop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Inhwa Jung, Moo-young Kim, Dongsuk Shin, Seon Wook Kim, Chulwoo Kim
2006	—	`conf`	An Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast Dynamic Voltage Scaling. CICC Janghoon Song, Gilwon Yoon, Chulwoo Kim
2006	J	`jnl`	Evaluating and Improving a Self-Help Technical Support Web Site: Use of Focus Group Interviews. Int. J. Hum. Comput. Interact. Pilsung Choe, Chulwoo Kim, Mark R. Lehto, Xinran Lehto, Jan P. Allebach
2006	C	`conf`	High Performance and Area-Efficient Circuit-Switched Network on Chip Design. CIT Phi-Hung Pham, Yogendera Kumar, Chulwoo Kim
2005	—	`conf`	Differential Pass Transistor Pulsed Latch. SoCC Moo-young Kim, Inhwa Jung, Young-Ho Kwak, Sunghoon Ahn, Chulwoo Kim
2005	—	`conf`	Jaguar: A Compiler Infrastructure for Java Reconfigurable Computing. ICESS Youngsun Han, Seon Kim, Chulwoo Kim
2004	J	`jnl`	A CMOS self-regulating VCO with low supply sensitivity. IEEE J. Solid State Circuits In-Chul Hwang, Chulwoo Kim, Sung-Mo Kang
2004	Misc	`conf`	Charge-Sharing-Problem Reduced Split-Path Domino Logic. VLSI Design Seoksoo Yoon, Seok-Ryong Yoon, Seon Wook Kim, Chulwoo Kim
2003	J	`jnl`	Energy-efficient skewed static logic with dual Vt: design and synthesis. IEEE Trans. Very Large Scale Integr. Syst. Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang
2003	—	`conf`	Low Power Cache with Successive Tag Comparison Algorithm. PATMOS Tae-Chan Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim
2003	—	`conf`	Low Power Response Time Accelerator with Full Resolution for LCD Panel. PATMOS Tae-Chan Kim, Meejoung Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim
2003	—	`conf`	OpenMP and Compilation Issue in Embedded Applications. WOMPAT Jaegeun Oh, Seon Wook Kim, Chulwoo Kim
2002	J	`jnl`	A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator. IEEE J. Solid State Circuits Chulwoo Kim, In-Chul Hwang, Sung-Mo Kang
2002	J	`jnl`	A low-swing clock double-edge triggered flip-flop. IEEE J. Solid State Circuits Chulwoo Kim, Sung-Mo Kang
2001	—	`conf`	A low-power reduced swing single clock flip-flop. ISCAS (4) Chulwoo Kim, Sung-Mo Kang
2001	—	`conf`	Energy-efficient skewed static logic design with dual Vt. ISCAS (4) Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang
2001	—	`—`	Low-Power CMOS Circuits for High-Performance Deep Submicron System on a Chip Chulwoo Kim
2001	—	`conf`	New current-mode sense amplifiers for high density DRAM and PIM architectures. ISCAS (4) Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang
2000	C	`conf`	High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology. ICCD Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang
2000	C	`conf`	Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic. ISCAS Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang
1999	—	`conf`	NMOS Energy Recovery Logic. Great Lakes Symposium on VLSI Chulwoo Kim, Seung-Moon Yoo, Sung-Mo Kang