| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2015 | J | jnl |
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.
IEEE J. Solid State Circuits
|
| 2014 | — | conf |
ISSCC
|
| 2006 | A* | conf |
PerCom
|
| 2006 | B | conf |
SECON
|
| 2006 | C | conf |
BSN
|
| 2006 | B | conf |
SECON
|
| 2006 | Misc | conf |
SenSys
|
| 2005 | J | jnl |
IEEE Des. Test Comput.
|
| 2005 | B | conf |
SECON
|
| 2005 | — | conf |
IPSN
|
| 2005 | A | conf |
ICCAD
|
| 2004 | A | conf |
ISLPED
|
| 2003 | A | conf |
ISLPED
|