Chul-Hong Park

18 papers A* 1A 2Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2024 J jnl
PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Suhyeong Choi, Jinwook Jung, Andrew B. Kahng, Minsoo Kim, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon
2023 J jnl
PROBE3.0: A Systematic Framework for Design-Technology Pathfinding with Improved Design Enablement.
CoRR
Suhyeong Choi, Jinwook Jung, Andrew B. Kahng, Minsoo Kim, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon
2017 — conf
12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis.
ISSCC
Taejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park, Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Cho, Yongjae Choo, Jaeseung Choi
2011 — conf
Exploration of VLSI CAD researches for early design rule evaluation.
ASP-DAC
Chul-Hong Park, David Z. Pan, Kevin Lucas
2010 J jnl
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao
2010 J jnl
Layout Decomposition Approaches for Double Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao
2010 J jnl
Suppression of Edge Effects Based on Analytic Model for Leakage Current Reduction of Sub-40 nm DRAM Device.
IEICE Trans. Electron.
Soo-Han Choi, Young Hee Park, Chul-Hong Park, Sang Hoon Lee, Moon-Hyun Yoo, Jun Dong Cho, Gyu Tae Kim
2009 J jnl
Lens aberration aware placement for timing yield.
ACM Trans. Design Autom. Electr. Syst.
Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang
2008 A* conf
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction.
DAC
Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao
2008 J jnl
Fast Dual-Graph-Based Hotspot Filtering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrew B. Kahng, Chul-Hong Park, Xu Xu
2008 A conf
Layout decomposition for double patterning lithography.
ICCAD
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao
2008 — —
Lithography-driven design for manufacturing in nanometer- era VLSI
Chul-Hong Park
2007 J jnl
Detailed Placement for Enhanced Control of Resist and Etch CDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
2006 A conf
Lens aberration aware timing-driven placement.
DATE
Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang
2006 J jnl
Wafer Topography-Aware Optical Proximity Correction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu
2005 — conf
Detailed placement for improved depth of focus and CD control.
ASP-DAC
Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
2002 — conf
A Hybrid PPC Method Based on the Empirical Etch Model for the 0.14µm DRAM Generation and Beyond.
ISQED
Chul-Hong Park, Soo-Han Choi, Sang-Uhk Rhie, Dong-Hyun Kim, Jun-Seong Park, Tae-Hwang Jang, Ji-Soong Park, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong
2000 — conf
An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18mum ASIC.
ISQED
Ji-Soong Park, Chul-Hong Park, Sang-Uhk Rhie, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong, Hyung-Woo Kim, Sun-Il Yoo