Chuanjin Richard Shi

149 papers A* 9A 14B 1C 18Misc 4Journal 55Unranked 48

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A 225-μW Interference-Tolerant Receiver With Shared Wireless LO and Envelope-Tracking Mixer Achieving -104-dBm Sensitivity. IEEE J. Solid State Circuits Heyu Ren, Liangjian Lyu, Binbin Chen, Wenjun Gong, Xing Wu, Chuanjin Richard Shi
2025	C	`conf`	A 915MHz 97nW Low-Area Wake-Up Receiver with an Envelope-Tracking Mixer Achieving -73.2dBm Sensitivity. ISCAS Binbin Chen, Heyu Ren, Wenjun Gong, Liangjian Lyu, Chuanjin Richard Shi
2025	C	`conf`	A Reference Double-Sampling PLL-Based Eight Phase Clock Generator Achieving 0.18mW/GHz/phase and -251.9dB FOMJitter-N. ISCAS Sirou Li, Weijia Zeng, Kaiyun Cao, Liangjian Lyu, Chuanjin Richard Shi
2025	—	`conf`	HCSAs: Hybrid Computing Systolic Arrays for Accelerating Mamba Models with Unified State Space Buffers and Energy-Efficient Dataflow. ACM Great Lakes Symposium on VLSI Xu Jin, Haotian Zheng, Maohua Nie, Jialin Wang, Chuanjin Richard Shi
2024	—	`conf`	A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR. CICC Heyu Ren, Liangjian Lyu, Binbin Chen, Chuanjin Richard Shi
2024	J	`jnl`	Fall Detection System Based on Point Cloud Enhancement Model for 24 GHz FMCW Radar. Sensors Tingxuan Liang, Ruizhi Liu, Lei Yang, Yue Lin, Chuanjin Richard Shi, Hongtao Xu
2024	J	`jnl`	SSGCNet: A Sparse Spectra Graph Convolutional Network for Epileptic EEG Signal Classification. IEEE Trans. Neural Networks Learn. Syst. Jialin Wang, Rui Gao, Haotian Zheng, Hao Zhu, Chuanjin Richard Shi
2024	J	`jnl`	Timed-Elastic-Band Based Variable Splitting for Autonomous Trajectory Planning. CoRR Hao Zhu, Kefan Jin, Rui Gao, Jialin Wang, Chuanjin Richard Shi
2023	—	`conf`	A 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature Extraction. A-SSCC Jingsen Yang, Liangjian Lyu, Zirui Dong, Heyu Ren, Chuanjin Richard Shi
2023	—	`conf`	A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF. ESSCIRC Renze Gan, Liangjian Lyu, Chuanjin Richard Shi
2023	J	`jnl`	Accelerating Distributed GNN Training by Codes. IEEE Trans. Parallel Distributed Syst. Yanhong Wang, Tianchan Guan, Dimin Niu, Qiaosha Zou, Hongzhong Zheng, Chuanjin Richard Shi, Yuan Xie
2023	J	`jnl`	Augmenting aspect-level sentiment classification with distance-related local context input. J. Supercomput. Yongchuan Dong, Qiaosha Zou, Chuanjin Richard Shi
2023	J	`jnl`	AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yanhong Wang, Zihao Zhao, Xu Jin, Haotian Zheng, Maohua Nie, Qiaosha Zou, Chuanjin Richard Shi
2022	—	`conf`	A 0.021mm ISSCC Rongjin Xu, Dawei Ye, Sirou Li, Chuanjin Richard Shi
2022	J	`jnl`	A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction. Integr. Rongjin Xu, Dawei Ye, Chuanjin Richard Shi
2022	—	`conf`	A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range. CICC Renze Gan, Liangjian Lyu, Geng Mu, Chuanjin Richard Shi
2022	J	`jnl`	Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors. IEEE Trans. Circuits Syst. I Regul. Pap. Rongjin Xu, Dawei Ye, Chuanjin Richard Shi
2022	J	`jnl`	Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain". IEEE J. Solid State Circuits Dawei Ye, Rongjin Xu, Chuanjin Richard Shi
2022	J	`jnl`	SAIL: A Deep-Learning-Based System for Automatic Gait Assessment From TUG Videos. IEEE Trans. Hum. Mach. Syst. Yanhong Wang, Qiaosha Zou, Yanmin Tang, Qing Wang, Jing Ding, Xin Wang, Chuanjin Richard Shi
2022	J	`jnl`	The Spike Gating Flow: A Hierarchical Structure Based Spiking Neural Network for Online Gesture Recognition. CoRR Zihao Zhao, Yanhong Wang, Qiaosha Zou, Tie Xu, Fangbo Tao, Jiansong Zhang, Xiaoan Wang, Chuanjin Richard Shi, Junwen Luo, Yuan Xie
2021	C	`conf`	A Fully-Synthesizable Fast-Response Digital LDO Using Automatic Offset Control and Reuse. ISCAS Chang Liu, Chun Zhao, Chuanjin Richard Shi
2021	J	`jnl`	A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain. IEEE J. Solid State Circuits Dawei Ye, Rongjin Xu, Chuanjin Richard Shi
2021	—	`conf`	A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference. A-SSCC Dawei Ye, Yuting Tu, Wenjun Gong, Rongjin Xu, Chuanjin Richard Shi
2021	—	`conf`	An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording. CICC Geng Mu, Dawei Ye, Liangjian Lyu, Xiaobin Zhao, Chuanjin Richard Shi
2021	J	`jnl`	Design of the Class-E Power Amplifier Considering the Temperature Effect of the Transistor On-Resistance for Sensor Applications. IEEE Trans. Circuits Syst. II Express Briefs Chang Liu, Chuanjin Richard Shi
2021	J	`jnl`	Saliency-based YOLO for single target detection. Knowl. Inf. Syst. Junying Hu, Chuanjin Richard Shi, Jiang-She Zhang
2021	Misc	`conf`	Single-Pass On-Line Event Detection in Twitter Streams. ICMLC Xingfa Qiu, Qiaosha Zou, Chuanjin Richard Shi
2021	—	`conf`	Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time On-Device Speech Processing. ACM Great Lakes Symposium on VLSI Shiwei Liu, Zihao Zhao, Yanhong Wang, Qiaosha Zou, Yiyun Zhang, Chuanjin Richard Shi
2020	J	`jnl`	A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. Integr. Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi
2020	J	`jnl`	A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS. IEEE Trans. Biomed. Circuits Syst. Liangjian Lyu, Dawei Ye, Chuanjin Richard Shi
2020	C	`conf`	A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. ISCAS Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, Chuanjin Richard Shi
2020	J	`jnl`	A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. Haozhe Zhu, Chixiao Chen, Shiwei Liu, Qiaosha Zou, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Chuanjin Richard Shi
2020	J	`jnl`	A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. IEEE Trans. Circuits Syst. II Express Briefs Liangjian Lyu, Dawei Ye, Rongjin Xu, Geng Mu, Heng Zhao, Yingfei Xiang, Yuting Tu, Yiyun Zhang, Chuanjin Richard Shi
2020	J	`jnl`	A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation. IEEE J. Solid State Circuits Dawei Ye, Yu Wang, Yingfei Xiang, Liangjian Lyu, Hao Min, Chuanjin Richard Shi
2020	J	`jnl`	Analysis of Passive Charge Sharing-Based Segmented SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. Aili Wang, Chuanjin Richard Shi
2020	A	`conf`	ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM. DATE Yitu Wang, Fan Chen, Linghao Song, Chuanjin Richard Shi, Hai Helen Li, Yiran Chen
2020	J	`jnl`	Tanji: a General-purpose Neural Network Accelerator with Unified Crossbar Architecture. IEEE Des. Test Haozhe Zhu, Yu Wang, Chuanjin Richard Shi
2020	—	`conf`	XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping. AICAS Shiwei Liu, Haozhe Zhu, Chixiao Chen, Lihua Zhang, Chuanjin Richard Shi
2019	C	`conf`	A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. ISCAS Dawei Ye, Rongjin Xu, Liangjian Lyu, Chuanjin Richard Shi
2019	—	`conf`	A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity. ISSCC Dawei Ye, Rongjin Xu, Chuanjin Richard Shi
2019	C	`conf`	A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. ISCAS Liangjian Lyu, Dawei Ye, Chuanjin Richard Shi
2019	—	`conf`	A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time. CICC Aili Wang, Chixiao Chen, Chuanjin Richard Shi
2019	—	`conf`	A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. ASP-DAC Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi
2019	J	`jnl`	Analysis of Bitwise and Samplewise Switched Passive Charge Sharing SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. Chuanjin Richard Shi, Aili Wang
2019	A*	`conf`	Hierarchical Representation Learning for Bipartite Graphs. IJCAI Chong Li, Kunyang Jia, Dan Shen, Chuanjin Richard Shi, Hongxia Yang
2019	J	`jnl`	iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric. IEEE J. Emerg. Sel. Topics Circuits Syst. Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, Chuanjin Richard Shi
2018	J	`jnl`	A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS. Integr. Aili Wang, Chuanjin Richard Shi
2018	—	`conf`	A 13.56 MHz Active Rectifier With Self-Switching Comparator for Wireless Power Transfer Systems. ISOCC Yingfei Xiang, Yu Wang, Chuanjin Richard Shi
2018	—	`conf`	A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. ISSCC Yu Wang, Dawei Ye, Liangjian Lyu, Yingfei Xiang, Hao Min, Chuanjin Richard Shi
2018	—	`conf`	Constrained Optimization Based Low-Rank Approximation of Deep Neural Networks. ECCV (10) Chong Li, Chuanjin Richard Shi
2018	A*	`conf`	Exploring the programmability for deep learning processors: from architecture to tensorization. DAC Chixiao Chen, Huwan Peng, Xindi Liu, Hongwei Ding, Chuanjin Richard Shi
2018	J	`jnl`	OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Chixiao Chen, Hongwei Ding, Huwan Peng, Haozhe Zhu, Yu Wang, Chuanjin Richard Shi
2018	C	`conf`	Pin-Efficient 12-Bit 8-Wire 8-Level Permutation Coding for High-Speed Parallel Wireline Tranceivers. ISCAS Ailing Piao, Aili Wang, Chuanjin Richard Shi
2018	—	`conf`	iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS. ESSCIRC Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, Chuanjin Richard Shi
2017	J	`jnl`	A High-Efficiency Split-Merge Charge Pump for Solar Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs Yu Wang, Na Yan, Hao Min, Chuanjin Richard Shi
2017	J	`jnl`	Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. Aili Wang, Chixiao Chen, Chuanjin Richard Shi
2017	—	`conf`	OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators. ESSCIRC Chixiao Chen, Hongwei Ding, Huwan Peng, Haozhe Zhu, Rui Ma, Peiyong Zhang, Xiaolang Yan, Yu Wang, Mingyu Wang, Hao Min, Chuanjin Richard Shi
2016	C	`conf`	A sub-nW mV-range programmable threshold comparator for near-zero-energy sensing. ISCAS Aili Wang, Allen Waters, Chuanjin Richard Shi
2016	C	`conf`	Highly time-interleaved noise-shaped SAR ADC with reconfigurable order. ISCAS Allen Waters, Aili Wang, Chuanjin Richard Shi
2015	—	`conf`	Identifying DC bias conditions for maximum DC current in digitally-assisted analog design. ICECS Chong Li, Suriyaprakash Natarajan, Chuanjin Richard Shi
2010	C	`conf`	Mixed-signal system-on-chip verification using a recursively-verifying-modeling (RVM) methodology. ISCAS Chuanjin Richard Shi
2010	J	`jnl`	Symmetry-aware placement algorithm using transitive closure graph representation for analog integrated circuits. Int. J. Circuit Theory Appl. Lihong Zhang, Yuping Zhang, Yingtao Jiang, Chuanjin Richard Shi
2008	C	`conf`	A 6-11GHz multi-phase VCO design with active inductors. ISCAS Yu-Te Liao, Chuanjin Richard Shi
2008	C	`conf`	A quantum-dot light-harvesting architecture using deterministic phase control. ISCAS Cherry Wakayama, Wolf Kohn, Zelda B. Zabinsky, Chuanjin Richard Shi
2008	J	`jnl`	Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Chuanjin Richard Shi
2008	—	`conf`	Scalable Symbolic Model Order Reduction. BMAS Yiyu Shi, Lei He, Chuanjin Richard Shi
2008	J	`jnl`	Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bo Hu, Chuanjin Richard Shi
2008	J	`jnl`	Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Lingzhi Liu, Chuanjin Richard Shi
2008	—	`conf`	Symmetry-aware placement with transitive closure graphs for analog layout design. ASP-DAC Lihong Zhang, Chuanjin Richard Shi, Yingtao Jiang
2007	—	`conf`	A Graph Reduction Approach to Symbolic Circuit Analysis. ASP-DAC Guoyong Shi, Weiwei Chen, Chuanjin Richard Shi
2007	J	`jnl`	CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lili Zhou, Cherry Wakayama, Chuanjin Richard Shi
2007	C	`conf`	Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits. ICCD Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, Chuanjin Richard Shi
2007	C	`conf`	Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining. ICCD Ming Su, Lili Zhou, Chuanjin Richard Shi
2007	J	`jnl`	VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial. Integr. Pavel V. Nikitin, Chuanjin Richard Shi
2006	J	`jnl`	A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhao Li, Chuanjin Richard Shi
2006	—	`conf`	A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits. ASP-DAC Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, Chuanjin Richard Shi
2006	—	`conf`	A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings. ASP-DAC Zhao Li, Chuanjin Richard Shi
2006	J	`jnl`	Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder. IEEE Trans. Circuits Syst. I Regul. Pap. Lei Yang, Hui Liu, Chuanjin Richard Shi
2006	J	`jnl`	Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuanjin Richard Shi, Michael W. Tian, Guoyong Shi
2006	J	`jnl`	FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits. Integr. Lei Yang, Chuanjin Richard Shi
2006	C	`conf`	Improved automatic differentiation method for efficient model compiler. ISCAS Bo Hu, Chuanjin Richard Shi
2006	J	`jnl`	Multilevel symmetry-constraint generation for retargeting large analog layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Chuanjin Richard Shi
2006	J	`jnl`	On symbolic model order reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guoyong Shi, Bo Hu, Chuanjin Richard Shi
2006	J	`jnl`	SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhao Li, Chuanjin Richard Shi
2006	A	`conf`	Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. ICCAD Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, Chuanjin Richard Shi
2005	A	`conf`	An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation. DATE Zhao Li, Chuanjin Richard Shi
2005	—	`conf`	An FPGA implementation of low-density parity-check code decoder with multi-rate capability. ASP-DAC Lei Yang, Manyuan Shen, Hui Liu, Chuanjin Richard Shi
2005	Misc	`conf`	Automatic Device Layout Generation for Analog Layout Retargeting. VLSI Design Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Chuanjin Richard Shi
2005	—	`conf`	Bridging Circuits and Electromagnetics in a Curriculum Aimed at Microelectronic Analog and Microwave Simulation and Design. MSE Vikram Jandhyala, Yasuo Kuga, David J. Allstot, Chuanjin Richard Shi
2005	A	`conf`	Fast-yet-accurate PVT simulation by combined direct and iterative methods. ICCAD Bo Hu, Chuanjin Richard Shi
2005	—	`conf`	Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC. ISCAS (6) Bo Hu, Zhao Li, Lili Zhou, Chuanjin Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe
2005	J	`jnl`	Model-order reduction by dominant subspace projection: error bound, subspace computation, and circuit applications. IEEE Trans. Circuits Syst. I Regul. Pap. Guoyong Shi, Chuanjin Richard Shi
2005	—	`conf`	Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer. ACM Great Lakes Symposium on VLSI Lei Yang, Cherry Wakayama, Chuanjin Richard Shi
2005	A*	`conf`	Template-driven parasitic-aware optimization of analog integrated circuit layouts. DAC Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Chuanjin Richard Shi
2005	B	`conf`	VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity. GLOBECOM Lei Yang, Hui Liu, Chuanjin Richard Shi
2004	—	`conf`	A coupled iterative/direct method for efficient time-domain simulation of nonlinear circuits with power/ground networks. ISCAS (5) Zhao Li, Chuanjin Richard Shi
2004	—	`conf`	Circuit level modeling and simulation of mixed-technology systems. SoCC Bo Wan, Pavel V. Nikitin, Chuanjin Richard Shi
2004	A*	`conf`	Correct-by-construction layout-centric retargeting of large analog designs. DAC Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, Chuanjin Richard Shi
2004	—	`conf`	CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. ASP-DAC Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, Chuanjin Richard Shi
2004	J	`jnl`	Efficient approximation of symbolic expressions for analog behavioral modeling and analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sheldon X.-D. Tan, Chuanjin Richard Shi
2004	A	`conf`	Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation. DATE Bo Wan, Chuanjin Richard Shi
2004	—	`conf`	Hierarchical extraction and verification of symmetry constraints for analog layout automation. ASP-DAC Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, Chuanjin Richard Shi
2004	—	`conf`	Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow. ISQED Pavel V. Nikitin, Vikram Jandhyala, Daniel A. White, Nathan Champagne, John D. Rockway, Chuanjin Richard Shi, Chuanyi Yang, Yong Wang, Gong Ouyang, Rob Sharpe, John W. Rockway
2004	—	`conf`	Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting. ASP-DAC Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, Chuanjin Richard Shi
2004	—	`conf`	Parametric reduced order modeling for interconnect analysis. ASP-DAC Guoyong Shi, Chuanjin Richard Shi
2003	—	`conf`	Automatic analog layout retargeting for new processes and device sizes. ISCAS (4) Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, Chuanjin Richard Shi
2003	J	`jnl`	Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis. Integr. Sheldon X.-D. Tan, Chuanjin Richard Shi
2003	—	`conf`	Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis. ISCAS (4) Sambuddha Bhattacharya, Chuanjin Richard Shi
2003	J	`jnl`	Efficient DDD-Based Interpretable Symbolic Characterization of Large Analog Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sheldon X.-D. Tan, Chuanjin Richard Shi
2003	—	`conf`	Efficient DDD-based term generation algorithm for analog circuit behavioral modeling. ASP-DAC Sheldon X.-D. Tan, Chuanjin Richard Shi
2003	J	`jnl`	Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sheldon X.-D. Tan, Chuanjin Richard Shi
2003	A	`conf`	FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits. ICCAD Lei Yang, Chuanjin Richard Shi
2003	J	`jnl`	IPRAIL - intellectual property reuse-based analog IC layout automation. Integr. Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, Chuanjin Richard Shi
2003	—	`conf`	MCAST: an abstract-syntax-tree based model compiler for circuit simulation. CICC Bo Wan, Bo P. Hu, Lili Zhou, Chuanjin Richard Shi
2003	C	`conf`	Parametric Equivalent Circuit Extraction for VLSI Structures. VLSI-SOC Pavel V. Nikitin, Winnie Yam, Chuanjin Richard Shi
2003	J	`jnl`	Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sheldon X.-D. Tan, Chuanjin Richard Shi, Jyh-Chwen Lee
2003	A	`conf`	SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects. ICCAD Zhao Li, Chuanjin Richard Shi
2003	A	`conf`	Symbolic Analysis of Nonlinear Analog Circuits. DATE Alicia Manthe, Zhao Li, Chuanjin Richard Shi, Kartikeya Mayaram
2003	A*	`conf`	Symbolic analysis of analog circuits with hard nonlinearity. DAC Alicia Manthe, Zhao Li, Chuanjin Richard Shi
2002	—	`conf`	Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes. ISQED Vikram Jandhyala, Yong Wang, Dipanjan Gope, Chuanjin Richard Shi
2001	J	`jnl`	Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuanjin Richard Shi, Sheldon X.-D. Tan
2001	C	`conf`	Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits. ICCD Dragos Lungeanu, Chuanjin Richard Shi
2001	A*	`conf`	Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling. DAC Sheldon X.-D. Tan, Chuanjin Richard Shi
2001	C	`conf`	Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis. ICCD Alicia Manthe, Chuanjin Richard Shi
2000	—	`conf`	Analog-testability analysis by determinant-decision-diagrams based symbolic analysis. ASP-DAC Tao Pi, Chuanjin Richard Shi
2000	J	`jnl`	Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuanjin Richard Shi, Sheldon X.-D. Tan
2000	J	`jnl`	Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sheldon X.-D. Tan, Chuanjin Richard Shi
2000	A	`conf`	Layout Compaction for Yield Optimization via Critical Area Minimization. DATE Youcef Bourai, Chuanjin Richard Shi
2000	A*	`conf`	Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits. DAC Tao Pi, Chuanjin Richard Shi
2000	A	`conf`	Parallel and Distributed VHDL Simulation. DATE Dragos Lungeanu, Chuanjin Richard Shi
2000	—	`conf`	Symbolic circuit-noise analysis and modeling with determinant decision diagrams. ASP-DAC Xiang-Dong Tan, Chuanjin Richard Shi
1999	J	`jnl`	A Characterization of Signed Hypergraphs and Its Applications to VLSI Via Minimization and Logic Synthesis. Discret. Appl. Math. Chuanjin Richard Shi, Janusz A. Brzozowski
1999	—	`conf`	Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis. ASP-DAC Xiang-Dong Tan, Chuanjin Richard Shi
1999	A	`conf`	Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization. ICCAD Dragos Lungeanu, Chuanjin Richard Shi
1999	A	`conf`	Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams. DATE Xiang-Dong Tan, Chuanjin Richard Shi
1999	A*	`conf`	Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings. DAC Xiang-Dong Tan, Chuanjin Richard Shi, Dragos Lungeanu, Jyh-Chwen Lee, Li-Pen Yuan
1999	J	`jnl`	Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis. ACM Trans. Design Autom. Electr. Syst. Chuanjin Richard Shi, Michael W. Tian
1999	—	`conf`	Symmetry Detection for Automatic Analog-Layout Recycling. ASP-DAC Youcef Bourai, Chuanjin Richard Shi
1998	—	`conf`	Automatic Test Generation for Linear Analog Circuits under Parameter Variations. ASP-DAC Chuanjin Richard Shi, Michael W. Tian
1998	J	`jnl`	Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS. J. Electron. Test. Nihal J. Godambe, Chuanjin Richard Shi
1998	J	`jnl`	Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems. ACM Trans. Design Autom. Electr. Syst. Chuanjin Richard Shi, Janusz A. Brzozowski
1998	A	`conf`	Efficient DC Fault Simulation of Nonlinear Analog Circuits. DATE Michael W. Tian, Chuanjin Richard Shi
1998	—	`conf`	Efficient derivation of exact s-expanded symbolic expressions for behavioral modeling of analog circuits. CICC Chuanjin Richard Shi, Xiang-Dong Tan
1998	Misc	`conf`	Nonlinear Analog DC Fault Simulation by One-Step Relaxation. VTS Michael W. Tian, Chuanjin Richard Shi
1997	Misc	`conf`	Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS. VTS Nihal J. Godambe, Chuanjin Richard Shi
1997	A*	`conf`	Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances. DAC Michael W. Tian, Chuanjin Richard Shi
1997	A	`conf`	Symbolic analysis of large analog circuits with determinant decision diagrams. ICCAD Chuanjin Richard Shi, Xiang-Dong Tan
1995	—	`conf`	A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems. ASP-DAC Chuanjin Richard Shi, Janusz A. Brzozowski
1992	—	`conf`	Efficient constrained encoding for VLSI sequential logic synthesis. EURO-DAC Chuanjin Richard Shi, Janusz A. Brzozowski