Chuan Shan - RankMe

12 papers C 1Journal 2Unranked 8

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Dimitri Galayko, Chuan Shan, Eldar Zianbetov, Mohammad Javidan, Anton Korniienko, François Anceau, Olivier Billoint, Éric Colinet, Elena Blokhina, Jérôme Juillard
2016	—	`conf`	Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks. NEWCAS Eugene Koskin, Elena Blokhina, Chuan Shan, Eldar Zianbetov, Orla Feely, Dimitri Galayko
2015	—	`conf`	A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs. NEWCAS Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko
2014	C	`conf`	"Swimming pool"-like distributed architecture for clock generation in large many-core SoC. ISCAS Chuan Shan, François Anceau, Dimitri Galayko, Eldar Zianbetov
2014	—	`conf`	A reconfigurable distributed architecture for clock generation in large many-core SoC. ReCoSoC Chuan Shan, Dimitri Galayko, François Anceau, Eldar Zianbetov
2014	—	`—`	Distributed clock generator for globally and locally synchronous chips with a large size. (Générateur distribué d'horloge pour puces globalement et localement synchrones de grande taille). Chuan Shan
2013	J	`jnl`	A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC. Microelectron. J. Vincent Kerzerho, Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, Chuan Shan, G. Bontorin, Michel Renovell
2013	—	`conf`	Distributed clock generator for synchronous SoC using ADPLL network. CICC Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, Olivier Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard
2013	—	`conf`	FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. ReConFig Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko
2013	—	`conf`	On-chip clock error characterization for clock distribution system. ISVLSI Chuan Shan, Dimitri Galayko, François Anceau
2012	—	`conf`	Design and Modeling of ADPLL with sliding-window for wide range frequency tracking. NEWCAS Chuan Shan, Dimitri Galayko, François Anceau
2011	—	`conf`	FPGA implementation of reconfigurable ADPLL network for distributed clock generation. FPT Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet, Jérôme Juillard