Chua-Chin Wang

272 papers B 1C 44Journal 134Unranked 93

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 49.23% Power Reduction Active Gate Driver with Digital Multi-level Power Gating Control. J. Circuits Syst. Comput. Chua-Chin Wang, Pradyumna Vellanki, Soumika Majumder, L. S. S. Pavan Kumar Chodisetti, Venkata Naveen Kolakaluri, Mitch Ming-Chi Chou, Lean Karlo Santos Tolentino
2026	J	`jnl`	A 75.47 TOPS/W 4-kb Single-Ended SRAM-Based Compute-in-Memory Architecture Using 16-nm FinFET Technology. J. Signal Process. Syst. L. S. S. Pavan Kumar Chodisetti, Cheng-Yao Lo, Jeffrey Sean Walling, Yang Yi, Leenendra Chowdary Gunnam, Chua-Chin Wang
2025	—	`conf`	A 10-Bit 100 MS/s V ICICDT Pradyumna Vellanki, Yen-Jung Lin, U. Fat Chio, Chua-Chin Wang
2025	J	`jnl`	A 24.9% Power Reduction Active Gate Driver With Power Gating and Current Modulation for Power MOSFETs. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Pradyumna Vellanki, Wei-En Chiu, L. S. S. Pavan Kumar Chodisetti, Venkata Naveen Kolakaluri, Yun-Che Chang, Mitch Ming-Chi Chou
2025	J	`jnl`	A 4.447 mW at 100 MHz and 49.62% Uniqueness XNOR-XOR RO PUF ASIC Using 180-nm CMOS Process for IoT Security Applications. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Pradyumna Vellanki, Jian-Jie Chen, Ralph Gerard B. Sangalang
2025	—	`conf`	A 5 V ICICDT L. S. S. Pavan Kumar Chodisetti, Chen-Wei Yen, Pradyumna Vellanki, Yung Hung, Chua-Chin Wang
2025	J	`jnl`	A Power Transistor Active Gate Driver With Two-Level Miller Plateau Detection and Driving Device Equalization Using 180-nm HV BCD Process. IEEE Open J. Circuits Syst. Chua-Chin Wang, Pradyumna Vellanki, Venkata Naveen Kolakaluri, L. S. S. Pavan Kumar Chodisetti, Lean Karlo Santos Tolentino, Mitch Ming-Chi Chou, Oliver Lexter July Alvarez Jose
2025	J	`jnl`	A Power-Efficient 0.5668 TOPS/W Digital Logic Accelerator Implemented Using 40-nm CMOS Process for Underwater Object Recognition Usage. IEEE Access Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho
2025	J	`jnl`	An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process. Integr. Chua-Chin Wang, Pradyumna Vellanki, Shih-Heng Luo, Ralph Gerard B. Sangalang
2025	J	`jnl`	Up To 99.6 % duty cycle digital PWM using 180-nm CMOS process. Microelectron. J. Chua-Chin Wang, Oliver Lexter July Alvarez Jose, Venkata Naveen Kolakaluri
2024	J	`jnl`	A 1-6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD. Microelectron. J. Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Bo-Hao Liao, Pradyumna Vellanki, Tzung-Je Lee
2024	C	`conf`	A 10-MHz 5-V On-chip 6-layer Multi-level Digital Transformer Using T18HVG2 Process. ISCAS Oliver Lexter July A. Jose, Yun-Che Chang, Venkata Naveen Kolakaluri, Celso B. Co, Mitch Ming-Chi Chou, Chua-Chin Wang
2024	J	`jnl`	A 13.73 ns Input Time Range TDA Design Based on Adjustable Current Sources Using 40-nm CMOS Process. Circuits Syst. Signal Process. Chua-Chin Wang, Oliver Lexter July A. Jose, Li Lin, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Anela L. Salvador
2024	J	`jnl`	A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic. Integr. Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Pradyumna Vellanki
2024	—	`conf`	A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process. AICAS Cheng-Yao Lo, Lean Karlo Santos Tolentino, Jhih-Ying Ke, Jeffrey S. Walling, Yang Yi, Chua-Chin Wang
2024	—	`conf`	A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process. AICAS Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho
2024	J	`jnl`	A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Jhih-Ying Ke, Cheng-Yao Lo, Tzung-Je Lee, Lean Karlo Santos Tolentino
2024	J	`jnl`	A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. IEEE Trans. Very Large Scale Integr. Syst. Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang
2024	—	`conf`	A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD Process. ISOCC Soumika Majumder, Lean Karlo Santos Tolentino, Oliver Lexter July Alvarez Jose, Venkata Naveen Kolakaluri, Mitch Ming-Chi Chou, Chua-Chin Wang
2024	C	`conf`	A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process. ISCAS Soumika Majumder, Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang
2024	J	`jnl`	A single-chip PFM-controlled LED driver with 0.5% illuminance variation. Microelectron. J. Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Pang-Yen Lou, Chen-Cheng-Hung Hung, Pradyumna Vellanki, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tirso A. Ronquillo
2024	—	`conf`	Active Gate Driver Design Using Differential Timing-based Miller Detector for Power MOSFET. APCCAS Pradyumna Vellanki, Venkata Naveen Kolakaluri, Yun-Che Chang, L. S. S. Pavan Kumar Chodisetti, Mitch Ming-Chi Chou, Chua-Chin Wang
2024	—	`conf`	An On-chip Temperature Sensor with 1°C Resolution And Wide Detection Range Using 180-nm CMOS Process. ISOCC Pradyumna Vellanki, Hung-Che Tseng, Ying-Xuan Chen, L. S. S. Pavan Kumar Chodisetti, Chua-Chin Wang
2024	—	`conf`	GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process. AICAS Jhih-Ying Ke, Lean Karlo Santos Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang
2023	—	`conf`	2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETs. APCCAS Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Jui-Min Kuo, Mitch Ming-Chi Chou, Chua-Chin Wang
2023	—	`conf`	A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process. APCCAS Ralph Gerard B. Sangalang, Wei-Zhen Chen, Chua-Chin Wang
2023	J	`jnl`	A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process. IET Circuits Devices Syst. Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose
2023	J	`jnl`	A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. Circuits Syst. Signal Process. Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee
2023	—	`conf`	A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process. APCCAS Jhih-Ying Ke, Lean Karlo S. Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang
2023	J	`jnl`	A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs Ralph Gerard B. Sangalang, Shiva Reddy, Lean Karlo S. Tolentino, You-Wei Shen, Oliver Lexter July A. Jose, Chua-Chin Wang
2023	J	`jnl`	A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process. Integr. Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang
2023	—	`conf`	A 99.6 % Duty Cycle High-Resolution DPWM Using Reconfiguring Decoder. MWSCAS Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang
2023	—	`conf`	A High Resolution And Wide Range Temperature Detector Using 180-nm CMOS Process. ICICDT Ralph Gerard B. Sangalang, Shih-Heng Luo, Chua-Chin Wang
2023	C	`conf`	Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle. ISCAS Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang
2023	—	`conf`	Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS. ASICON Ralph Gerard B. Sangalang, You-Wei Shen, Shiva Reddy, Lean Karlo S. Tolentino, Chua-Chin Wang
2023	—	`conf`	SiC MOSFET High Side Gate Driver Design Using HV CMOS Process. MWSCAS Oliver Lexter July A. Jose, Jui-Min Kuo, Venkata Naveen Kolakaluri, Chua-Chin Wang
2022	C	`conf`	A 40-nm CMOS Wide Input Range and Variable Gain Time-Difference Amplifier Based on Current Source Architecture. ISCAS Li Lin, Lean Karlo S. Tolentino, Chua-Chin Wang
2022	J	`jnl`	A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. Chua-Chin Wang, Ralph Gerard B. Sangalang, Chien-Ping Kuo, Hsin-Che Wu, Yi Hsu, Shen-Fu Hsiao, Chia-Hung Yeh
2022	—	`conf`	A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology. APCCAS Jyoshnavi Akiri, Lean Karlo S. Tolentino, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang
2022	—	`conf`	A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic. ICICDT Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang
2022	—	`conf`	A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter Module. APCCAS Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Chua-Chin Wang
2022	—	`conf`	A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture. APCCAS Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu
2022	J	`jnl`	Lightweight Deep Neural Network for Joint Learning of Underwater Object Detection and Color Conversion. IEEE Trans. Neural Networks Learn. Syst. Chia-Hung Yeh, Chu-Han Lin, Li-Wei Kang, Chih-Hsiang Huang, Min-Hui Lin, Chuan-Yu Chang, Chua-Chin Wang
2022	—	`conf`	Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process. ICICDT Shiva Reddy, Ralph Gerard B. Sangalang, Chua-Chin Wang
2022	—	`conf`	Wide Lock-in Range CDR with Modified DQFD and Coarse-fine Tuning Technique. ICICDT Tzung-Je Lee, Bo-Hao Liao, Chua-Chin Wang
2021	J	`jnl`	0.7 % error rate 3A bidirectional current sensor using high voltage CMOS process. Microelectron. J. Chua-Chin Wang, Pang-Yen Lou, Zong-You Hou, Hsiu-Chun Tsai
2021	J	`jnl`	200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Chien-Ping Kuo
2021	J	`jnl`	2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process. Circuits Syst. Signal Process. Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Yan-You Chou, Tzung-Je Lee
2021	C	`conf`	67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process. ISCAS Chua-Chin Wang, Chien-Ping Kuo
2021	C	`conf`	A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop. ISCAS Uday Kiran Naidu Ekkurthi, Venkatesh Dasari, Jyoshnavi Akiri, Chua-Chin Wang
2021	—	`conf`	A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment. APCCAS Tzung-Je Lee, Wen-Jian Su, Lean Karlo S. Tolentino, Chua-Chin Wang
2021	—	`conf`	A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology. APCCAS Tzung-Je Lee, Wen-Shou Yang, Chua-Chin Wang
2021	J	`jnl`	A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Lean Karlo S. Tolentino, Chia-Yi Huang, Chia-Hung Yeh
2021	J	`jnl`	A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng
2021	—	`conf`	An AI AUV Enabling Vision-based Diver-following and Obstacle Avoidance with 3D-modeling Dataset. AICAS Yu-Cheng Chou, Hsin-Hung Chen, Chau-Chang Wang, Hui-Min Chou, Chua-Chin Wang
2021	J	`jnl`	An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS. Microelectron. J. Chua-Chin Wang, Oliver Lexter July A. Jose, Po-Kai Su, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Jessica Velasco, Tzung-Je Lee
2021	—	`conf`	Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer. ISOCC Pang-Yen Lou, Yung-Yuan Ho, Chua-Chin Wang
2021	J	`jnl`	High-Accuracy Impedance Read-out Circuit for BIA-type Biomedical Sensors. Circuits Syst. Signal Process. Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, I-Yu Huang, Yu-Cheng Lin, Tzung-Je Lee, Guan-Ru Chen
2021	—	`conf`	On-chip CMOS Corner Detector Design for Panel Drivers. ISOCC Pang-Yen Lou, Ying-Xuan Chen, Chua-Chin Wang
2021	C	`conf`	SRAM-Based Computation in Memory Architecture to Realize Single Command of Add-Multiply Operation and Multifunction. ISCAS Chua-Chin Wang, Chia-Yi Huang, Chia-Hung Yeh
2021	J	`jnl`	Tutorial: Design of High-Speed Nano-Scale CMOS Mixed-Voltage Digital I/O Buffer With High Reliability to PVTL Variations. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang
2020	—	`conf`	100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches APCCAS Chua-Chin Wang, Shao-Wei Lu
2020	J	`jnl`	2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations. J. Circuits Syst. Comput. Chua-Chin Wang, Zong-You Hou, Yu-Lin Deng, U. Fat Chio, Wei Wang
2020	—	`conf`	3D-Modeling Dataset Augmentation for Underwater AUV Real-time Manipulations. APCCAS Chua-Chin Wang, Chia-Yi Huang, Chu-Han Lin, Chia-Hung Yeh, Guan-Xian Liu, Yu-Cheng Chou
2020	J	`jnl`	A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry. J. Circuits Syst. Comput. Chua-Chin Wang, Zong-You Hou, Deng-Shian Wang, Chia-Lung Hsieh
2020	J	`jnl`	A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique. IEEE Trans. Circuits Syst. Tzung-Je Lee, Ssu-Wei Huang, Chua-Chin Wang
2020	J	`jnl`	Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Kuan-Yu Chao, Sivaperumal Sampath, Ponnan Suresh
2020	J	`jnl`	Power-effective ROM-less DDFS Design Approach with High SFDR Performance. J. Signal Process. Syst. Chua-Chin Wang, Nanang Sulistiyanto, Hsiang-Yu Shih, Yu-Cheng Lin, Wei Wang
2019	J	`jnl`	500 MHz 90 nm CMOS 2 \(\times \) VDD Digital Output Buffer Immunity to Process and Voltage Variations. Circuits Syst. Signal Process. Chua-Chin Wang, Tsung-Yi Tsai, Yu-Lin Deng, Tzung-Je Lee
2019	J	`jnl`	74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Hsiang-Yu Shih
2019	C	`conf`	A 1.5A 88.6% Li-ion Battery Charger Design using Pulse Swallow Technique in Light Load. ISCAS Chua-Chin Wang, Guan-Xian Liu
2019	C	`conf`	A Broken Line Detection Circuit for Multi-cell Li-ion Battery Module ICCE Pang-Yen Lou, Chien-Hua Chu, Chua-Chin Wang
2019	—	`conf`	A Low Frequency OTA Design with Temperature-Insensitive Variable Transconductance Using 180-nm CMOS Technology. ICICDT Nanang Sulistiyanto, Chua-Chin Wang, Robert Rieger
2019	—	`conf`	A PVT Validation Phase-Lock Loop with Multi-Band VCO Applied in Closed-Loop FOGs. ICICDT Tsung-Yi Tsai, Ting-Sheng Wang, Yi-Jen Chiu, Chua-Chin Wang
2019	J	`jnl`	A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method. IEEE Trans. Circuits Syst. II Express Briefs Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U. Fat Chio, Chua-Chin Wang
2019	C	`conf`	High Efficiency Buck Converter with Wide Load Current Range using Dual-Mode of PWM and PSM. ISCAS Tzung-Je Lee, Chia-Hsin Hsu, Chua-Chin Wang
2019	—	`conf`	Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems. ASICON Chun-Ting Chen, Tsung-Yi Tsai, Yi-Jen Chiu, Chua-Chin Wang
2019	—	`conf`	Ultra Low Power Single-ended 6T SRAM Using 40 nm CMOS Technology. ICICDT Chua-Chin Wang, I-Ting Tseng
2018	—	`conf`	40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate. APCCAS Chua-Chin Wang, Zong-You Hou, Ssu-Wei Huang
2018	J	`jnl`	A High-Precision CMOS Temperature Sensor with Thermistor Linear Calibration in the (-5 °C, 120 °C) Temperature Range. Sensors Chua-Chin Wang, Zong-You Hou, Jhih-Cheng You
2018	J	`jnl`	A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits. Circuits Syst. Signal Process. Chua-Chin Wang, Zong-You Hou, Chih-Lin Chen, Doron Shmilovitz
2018	C	`conf`	A frequency-shift readout system with offset cancellation OPA for portable devices of marijuana detection. ICCE Hao-Chun Huang, Deng-Shian Wang, Chua-Chin Wang
2017	J	`jnl`	2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Zong-You Hou, Kai-Wei Ruan
2017	J	`jnl`	A 19.38 dBm OIP3 gm-boosted up-conversion CMOS mixer for 5-6 GHz application. Microelectron. J. Wen-Hui Huang, I-Yu Huang, Yu-Shan Tseng, Chia-Hsu Hsieh, Chua-Chin Wang
2017	J	`jnl`	A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer. IEEE Trans. Very Large Scale Integr. Syst. Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U-Fat Chio, Chua-Chin Wang
2017	—	`conf`	A pipeline ROM-less DDFS using equal-division interpolation. ISOCC Tsung-Yi Tsai, Hsiang-Yu Shih, Chua-Chin Wang
2017	C	`conf`	A primary-side output current estimator with process compensator for flyback LED drivers. ISCAS Zong-You Hou, Zong-Ying Ho, Jhih-Cheng You, Chua-Chin Wang
2017	J	`jnl`	A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM. Microelectron. J. Deng-Shian Wang, Yu-Hsun Su, Chua-Chin Wang
2017	—	`conf`	Dynamic power estimation for ROM-less DDFS designs using switching activity analysis. ISOCC Wei Wang, Yuan-Yuan Xu, Chua-Chin Wang
2017	—	`conf`	High-voltage bidirectional current sensor. ASICON Zong-You Hou, Hsiu-Chun Tsai, Chua-Chin Wang
2017	J	`jnl`	Highly Sensitive FPW-Based Microsystem for Rapid Detection of Tetrahydrocannabinol in Human Urine. Sensors Je-Wei Lan, Chia-Hsu Hsieh, I-Yu Huang, Yu-Cheng Lin, Tsung-Yi Tsai, Chua-Chin Wang
2017	C	`conf`	State of charge, state of health, and state of function monitoring for EV BMS. ICCE Zong-You Hou, Pang-Yen Lou, Chua-Chin Wang
2016	J	`jnl`	A Leakage Compensation Design for Low Supply Voltage SRAM. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Deng-Shian Wang, Chiang-Hsiang Liao, Sih-Yu Chen
2016	C	`conf`	A flyback driver with adaptive switching frequency control for smart lighting1. ICCE Chua-Chin Wang, Zong-You Hou, Teng-Wei Huang
2016	—	`conf`	A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above. ICICDT Tsung-Yi Tsai, Yan-You Chou, Chua-Chin Wang
2016	C	`conf`	A nano-scale 2×VDD I/O buffer with encoded PV compensation technique. ISCAS Tsung-Yi Tsai, Yu-Lin Teng, Chua-Chin Wang
2016	—	`conf`	A novel frequency-shift readout system for CEA concentration detection application. ISOCC Deng-Shian Wang, Yun-Shen Liu, Chua-Chin Wang
2016	C	`conf`	An accurate phase shift detector using bulk voltage boosting technique for sensing applications. ISCAS Yu-Ting Tu, Deng-Shian Wang, Chua-Chin Wang
2016	—	`conf`	Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process. ISOCC Chua-Chin Wang, Chia-Lung Hsieh
2016	J	`jnl`	High-voltage on-chip current sensor design and analysis for battery modules. IET Circuits Devices Syst. Chua-Chin Wang, Zong-You Hou, Wen-Je Lu, Sheng-Syong Wang
2016	—	`conf`	On-chip accurate primary-side output current estimator for flyback LED driver control. ICICDT Zong-You Hou, Teng-Wei Huang, Chua-Chin Wang
2015	—	`conf`	10 Mbps high-voltage digital transciever on single die for 50 V voltage swing. ASICON Chua-Chin Wang, Min-Yu Tseng
2015	J	`jnl`	A 30 V rail-to-rail operational amplifier. Microelectron. J. Chua-Chin Wang, Tsung-Yi Tsai, Wen-Je Lu, Chih-Lin Chen, Yi-Lun Wu
2015	J	`jnl`	A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Chua-Chin Wang, Chih-Lin Chen, Zong-You Hou, Yi Hu, Jam-Wem Lee, Wan-Yen Lin, Yi-Feng Chang, Chia-Wei Hsu, Ming-Hsiang Song
2015	J	`jnl`	A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems. IEEE Trans. Very Large Scale Integr. Syst. Chih-Lin Chen, Deng-Shian Wang, Jie-Jyun Li, Chua-Chin Wang
2015	—	`conf`	A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology. ICICDT Chua-Chin Wang, Tsung-Yi Tsai, Wei Lin
2015	C	`conf`	A high-voltage Transceiver for electrical vehicle Battery Management Systems. ICCE Chih-Lin Chen, Deng-Shian Wang, Jie-Jyun Li, Chua-Chin Wang
2015	—	`conf`	A wide range and high conversion gain power detector for frequency shift sensing applications. MWSCAS Chua-Chin Wang, Deng-Shian Wang, Shiou-Ya Chen, Chia-Ming Chang
2015	J	`jnl`	A ±3.07% frequency variation clock generator implemented using HV CMOS process. Microelectron. J. Chua-Chin Wang, Deng-Shian Wang, Tzu-Chiao Sung, Yi-Jie Hsieh, Tzung-Je Lee
2015	J	`jnl`	Analysis of Calibrated On-Chip Temperature Sensor With Process Compensation for HV Chips. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Wen-Je Lu, Tsung-Yi Tsai
2015	J	`jnl`	Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology. Microelectron. J. Chua-Chin Wang, Wen-Je Lu, Kai-Wei Juan, Wei Lin, Hsin-Yuan Tseng, Chun-Ying Juan
2015	J	`jnl`	Wide-range CTAT and PTAT sensors with second-order calibration for on-chip thermal monitoring. Microelectron. J. Chua-Chin Wang, Wen-Je Lu, Tzu-Chao Wu
2014	—	`conf`	32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation. ICICDT Tzung-Je Lee, Kai-Wei Ruan, Chua-Chin Wang
2014	—	`conf`	A 20 GHz power detector with 176 mV/dB conversion gain. APCCAS Chua-Chin Wang, Deng-Shian Wang, Shiou-Ya Chen, Chia-Ming Chang
2014	C	`conf`	A CMOS wide-range temperature sensor with process compensation and second-order calibration for Battery Management Systems. ISCAS Chua-Chin Wang, Wen-Je Lu, Tzu-Chao Wu, Chun-Ying Juan
2014	J	`jnl`	A FlexRay Transceiver Design with Bus Guardian for In-car Networking Systems Compliant with FlexRay Standard. J. Signal Process. Syst. Chua-Chin Wang, Chih-Lin Chen, Gang-Neng Sung, Ching-Lin Wang, Chun-Ying Juan
2014	C	`conf`	A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm CMOS process. ISCAS Chua-Chin Wang, Chiang-Hsiang Liao, Sih-Yu Chen
2014	—	`conf`	An all-digital battery capacity monitor using calibrated current estimation approach. APCCAS Chua-Chin Wang, Wen-Je Lu, Min-Yu Tseng
2014	—	`conf`	An on-chip high-voltage current sensor for battery module monitoring. ICICDT Chua-Chin Wang, Wen-Je Lu, Sheng-Syong Wang
2014	J	`jnl`	Noninvasive Control of the Power Transferred to an Implanted Device by an Ultrasonic Transcutaneous Energy Transfer Link. IEEE Trans. Biomed. Eng. Doron Shmilovitz, Shaul Ozeri, Chua-Chin Wang, Boaz Spivak
2013	J	`jnl`	A 2×VDD output buffer with PVT detector for slew rate compensation. Microelectron. J. Chua-Chin Wang, Wen-Je Lu, Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chun-Ying Juan
2013	J	`jnl`	A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. Chua-Chin Wang, Chih-Lin Chen, Hsin-Yuan Tseng, Hsiao-Han Hou, Chun-Ying Juan
2013	J	`jnl`	A Protein Concentration Measurement System Using a Flexural Plate-Wave Frequency-Shift Readout Technique. Sensors Chua-Chin Wang, Tzu-Chiao Sung, Chia-Hao Hsu, Yue-Da Tsai, Yun-Chi Chen, Ming-Chih Lee, I-Yu Huang
2013	C	`conf`	A delay-based transceiver with over-current protection for ECU nodes in automobile FlexRay systems. ICCE Chih-Lin Chen, Zong-You Hou, Sheng-Chih Lin, Chua-Chin Wang
2013	C	`conf`	A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology. ISCAS Chua-Chin Wang, Wen-Je Lu, Hsin-Yuan Tseng
2013	J	`jnl`	A low-power transceiver design for FlexRay-based communication systems. Microelectron. J. Chua-Chin Wang, Chih-Lin Chen, Jie-Jyun Li, Gang-Neng Sung, Tai-Hao Yeh, Chun-Ying Juan
2013	—	`conf`	High voltage operational amplifier and high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems. ICICDT Chih-Lin Chen, Yi-Lun Wu, Chun-Ying Juan, Chua-Chin Wang
2013	J	`jnl`	On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2, ×, VDD Output Buffers. IEEE Trans. Circuits Syst. I Regul. Pap. Chua-Chin Wang, Chih-Lin Chen, Ron-Chi Kuo, Hsin-Yuan Tseng, Jen-Wei Liu, Chun-Ying Juan
2012	—	`conf`	A Battery Interconnect Module with high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems. ISOCC Chih-Lin Chen, Deng-Shian Wang, Jie-Jyun Li, Chua-Chin Wang
2012	C	`conf`	A PLC transceiver design of in-vehicle power line in FlexRay-based automotive communication systems. ICCE Gang-Neng Sung, Chun-Ming Huang, Chua-Chin Wang
2012	J	`jnl`	A Signed Array Multiplier with Bypassing Logic. J. Signal Process. Syst. Chua-Chin Wang, Chia-Hao Hsu, Gang-Neng Sung, Yu-Cheng Lu
2012	J	`jnl`	A Single-Chip 60-V Bulk Charger for Series Li-Ion Batteries With Smooth Charge-Mode Transition. IEEE Trans. Circuits Syst. I Regul. Pap. Shang-Hsien Yang, Jen-Wei Liu, Chua-Chin Wang
2012	C	`conf`	A digital over-temperature protector for FlexRay systems. ISCAS Chih-Lin Chen, Sheng-Chih Lin, Chua-Chin Wang, Chun-Ying Juan
2012	C	`conf`	A fast FPW allergy analyzer prototype for point of care (POC). ICCE Chia-Hao Hsu, Yue-Da Tsai, Yun-Chi Chen, Ming-Chih Lee, I-Yu Huang, Chua-Chin Wang
2012	C	`conf`	A fast FPW-based protein concentration measurement system. ISCAS Chua-Chin Wang, Chia-Hao Hsu, Yue-Da Tsai, Yun-Chi Chen, Ming-Chih Lee, I-Yu Huang
2012	—	`conf`	A high voltage analog multiplexer with digital calibration for battery management systems. ICICDT Chih-Lin Chen, Yi Hu, Wayne Luo, Chua-Chin Wang, Chun-Ying Juan
2012	J	`jnl`	A low power 48-dB/stage linear-in-dB variable gain amplifier for direct-conversion receivers. Microelectron. J. Shang-Hsien Yang, Chua-Chin Wang
2012	—	`conf`	A reconfigurable 16-channel HV stimulator ASIC for Spinal Cord Stimulation systems. APCCAS Chua-Chin Wang, Tzu-Chiao Sung, Yihong Wu, Chia-Hao Hsu, Doron Shmilovitz
2012	—	`conf`	A slew rate self-adjusting 2×VDD output buffer With PVT compensation. VLSI-DAT Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang
2012	C	`conf`	Configurable Active Star design for automobile FlexRay systems. ICCE Chua-Chin Wang, Chih-Lin Chen, Jie-Jyun Li, Chun-Ying Juan
2012	J	`jnl`	Feed-forward Output Swing Prediction AGC design with Parallel-Detect Singular-Store Peak Detector. Microelectron. J. Shang-Hsien Yang, Chua-Chin Wang
2012	C	`conf`	Feed-forward Output Swing Prediction AGC with Parallel-Detect Singular-Store Peak Detector. ISCAS Shang-Hsien Yang, Chua-Chin Wang
2012	—	`conf`	Linear programmable gain amplifier using reconfiguration local-feedback transconductors. APCCAS Tzung-Je Lee, Wen-Je Lu, Wei-Chih Hsiao, Chua-Chin Wang
2012	—	`conf`	On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers. ICICDT Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang
2012	—	`conf`	Single-ended disturb-free 5T loadless SRAM Cell using 90 nm CMOS process. ICICDT Sih-Yu Chen, Chua-Chin Wang
2012	—	`conf`	Temperature and process compensated clock generator using feedback TPC bias. ICICDT Tzung-Je Lee, Doron Shmilovitz, Yi-Jie Hsieh, Chua-Chin Wang
2011	—	`conf`	A 48-dB dynamic gain range/stage linear-in-dB low power Variable Gain Amplifier for direct-conversion receivers. ISOCC Shang-Hsien Yang, Chua-Chin Wang
2011	J	`jnl`	A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset. J. Signal Process. Syst. Chua-Chin Wang, Chia-Hao Hsu, Chia-Chuan Lee, Jian-Ming Huang
2011	J	`jnl`	A Wide Voltage Range Digital I/O Design Using Novel Floating N-Well Circuit. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Chia-Hao Hsu, Szu-Chia Liao, Yi-Cheng Liu
2011	J	`jnl`	A high precision low dropout regulator with nested feedback loops. Microelectron. J. Chua-Chin Wang, Ron-Chi Kuo, Tung-Han Tsai
2011	C	`conf`	A high speed transceiver front-end design with fault detection for FlexRay-based automotive communication systems. ISCAS Chua-Chin Wang, Chih-Lin Chen, Tai-Hao Yeh, Yi Hu, Gang-Neng Sung
2011	C	`conf`	A high voltage battery charger with smooth charge mode transition in BCD process. ISCAS Shang-Hsien Yang, Jen-Wei Liu, Yihong Wu, Deng-Sian Wang, Chua-Chin Wang
2011	J	`jnl`	A high-efficiency DC-DC buck converter for sub-2×VDD power supply. Microelectron. J. Chua-Chin Wang, Chih-Lin Chen, Gang-Neng Sung, Ching-Lin Wang
2011	J	`jnl`	One-Time-Implantable Spinal Cord Stimulation System Prototype. IEEE Trans. Biomed. Circuits Syst. Chia-Hao Hsu, Shao-Bin Tseng, Yi-Jie Hsieh, Chua-Chin Wang
2010	J	`jnl`	(1/3) times hboxVDD-to- (3/2) times hboxVDD Wide-Range I/O Buffer Using 0.35- muhboxm 3.3-V CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Chi-Chun Huang, Tzung-Je Lee, Wei-Chih Chang, Chua-Chin Wang
2010	J	`jnl`	0.9 V to 5 V Bidirectional Mixed-Voltage I/O Buffer With an ESD Protection Output Stage. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Ron-Chi Kuo, Jen-Wei Liu
2010	J	`jnl`	A 1/2 times hbox VDD to 3 times hbox VDD Bidirectional I/O Buffer With a Dynamic Gate Bias Generator. IEEE Trans. Circuits Syst. I Regul. Pap. Chua-Chin Wang, Chia-Hao Hsu, Yi-Cheng Liu
2010	C	`conf`	A 125-MHz wide-range mixed-voltage I/O buffer using gated Floating N-well circuit. ISCAS Chua-Chin Wang, Szu-Chia Liao, Yi-Cheng Liu
2010	—	`conf`	A PCI166-compatible 3×VDD-tolerant mixed-voltage I/O buffer. APCCAS Ron-Chi Kuo, Hsiao-Han Hou, Chua-Chin Wang
2010	J	`jnl`	A Self-Disabled Sensing Technique for Content-Addressable Memories. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Chia-Hao Hsu, Chi-Chun Huang, Jun-Han Wu
2010	J	`jnl`	A Transceiver Front End for Electronic Control Units in FlexRay-Based Automotive Communication Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Chua-Chin Wang, Gang-Neng Sung, Po-Cheng Chen, Chin-Long Wey
2010	—	`conf`	A high precision low dropout regulator with nested feedback loops. APCCAS Ron-Chi Kuo, Tung-Han Tsai, Yi-Jie Hsieh, Chua-Chin Wang
2010	J	`jnl`	A low-power 2.45 GHz WPAN modulator/demodulator. Microelectron. J. Chua-Chin Wang, Gang-Neng Sung, Jian-Ming Huang, Lung-Hsuan Lee, Chih-Peng Li
2010	C	`conf`	A mini-invasive multi-function biomedical pressure measurement system ASIC. ISCAS Chua-Chin Wang, Chi-Chun Huang, Yi-Cheng Liu, Victor Pikov, Doron Shmilovitz
2010	J	`jnl`	All-Digital Frequency Synthesizer Using a Flying Adder. IEEE Trans. Circuits Syst. II Express Briefs Gang-Neng Sung, Szu-Chia Liao, Jian-Ming Huang, Yu-Cheng Lu, Chua-Chin Wang
2010	J	`jnl`	Energy-Efficient Double-Edge Triggered Flip-Flop. J. Signal Process. Syst. Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen
2010	J	`jnl`	Guest Editorial Special Issue on ISCAS 2009. IEEE Trans. Circuits Syst. I Regul. Pap. Chua-Chin Wang, Felix Lustenberger, Yehia Massoud, Wouter A. Serdijn
2010	J	`jnl`	Self-Sampled All-MOS ASK Demodulator for Lower ISM Band Applications. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Chih-Lin Chen, Ron-Chi Kuo, Doron Shmilovitz
2009	C	`conf`	A Drive Circuit for Piezoelectric Devices with Low Harmonics Content. ISCAS Shaul Ozeri, Doron Shmilovitz, Chua-Chin Wang
2009	J	`jnl`	Baseband Receiver Design for the MBOA Ultra Wideband Wireless Personal Area Networks. IEICE Trans. Commun. Sen-Hung Wang, Chih-Peng Li, Chao-Tang Yu, Jian-Ming Huang, Chua-Chin Wang
2009	J	`jnl`	Low-Power Multiplier Design Using a Bypassing Technique. J. Signal Process. Syst. Chua-Chin Wang, Gang-Neng Sung
2009	C	`conf`	Low-power 7.2 GHz Complementary All-N-Transistor Logic using 90 nm CMOS Technology. ISCAS Chia-Hao Hsu, Gang-Neng Sung, Tuo-Yu Yao, Chun-Ying Juan, Yain-Reu Lin, Chua-Chin Wang
2009	J	`jnl`	Wide-Range 5.0/3.3/1.8-V I/O Buffer Using 0.35-m 3.3-V CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Tzung-Je Lee, Tieh-Yen Chang, Chua-Chin Wang
2008	J	`jnl`	A 1.7-ns Access Time SRAM Using Variable Bulk Bias wordline-Controlled transistors. J. Circuits Syst. Comput. Chua-Chin Wang, Gang-Neng Sung, Chi-Chun Huang, Ching-Li Lee, Tian-Hau Chen, Wun-Ji Lin, Ron Hu
2008	—	`conf`	A 32-bit carry lookahead adder design using complementary all-N-transistor logic. ICECS Gang-Neng Sung, Chun-Ying Juan, Chua-Chin Wang
2008	J	`jnl`	A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants. Microelectron. J. Chua-Chin Wang, Tzung-Je Lee, U. Fat Chio, Yu-Tzu Hsiao, Jia-Jin Chen
2008	—	`conf`	A Li-ion battery charging design for biomedical implants. APCCAS Chi-Chun Huang, Shou-Fu Yen, Chua-Chin Wang
2008	J	`jnl`	A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng
2008	J	`jnl`	A Mini-Invasive Long-Term Bladder Urine Pressure Measurement ASIC and System. IEEE Trans. Biomed. Circuits Syst. Chua-Chin Wang, Chi-Chun Huang, Jian-Sing Liou, Yan-Jhin Ciou, I-Yu Huang, Chih-Peng Li, Yung-Chin Lee, Weng-Jeng Wu
2008	J	`jnl`	A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators. VLSI Design Tzung-Je Lee, Chua-Chin Wang
2008	—	`conf`	A ROM-less DDFS using a nonlinear DAC with an error compensation current array. APCCAS Chua-Chin Wang, Chia-Hao Hsu, Tuo-Yu Yao, Jian-Ming Huang
2008	—	`conf`	A ROM-less direct digital frequency synthesizer based on 16-segment parabolic polynomial interpolation. ICECS Jian-Ming Huang, Chia-Chuan Lee, Chua-Chin Wang
2008	J	`jnl`	A low-power ADPLL using feedback DCO quarterly disabled in time domain. Microelectron. J. Chua-Chin Wang, Chi-Chun Huang, Sheng-Lun Tseng
2008	C	`conf`	A mini-invasive multi-function bladder urine pressure measurement system. ISCAS Chua-Chin Wang, Chi-Chun Huang, Jun-Han Wu, I-Yu Huang
2008	C	`conf`	A power-aware 2-dimensional bypassing multiplier using cell-based design flow. ISCAS Gang-Neng Sung, Yan-Jhin Ciou, Chua-Chin Wang
2008	—	`conf`	A self-disable sense technique with differential NAND cell for content-addressable memories. ICECS Chi-Chun Huang, Jun-Han Wu, Chua-Chin Wang
2008	J	`jnl`	A single-chip CMOS IF-band converter design for DVB-T receivers. Microelectron. J. Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Chien-Chih Hung, Li-Pin Lin
2008	J	`jnl`	All-MOS ASK Demodulator for Low-Frequency Applications. IEEE Trans. Circuits Syst. II Express Briefs Tzung-Je Lee, Ching-Li Lee, Yan-Jhin Ciou, Chi-Chun Huang, Chua-Chin Wang
2008	—	`conf`	Mixed-voltage I/O buffer using 0.35 μm CMOS technology. ICECS Tzung-Je Lee, Wei-Chih Chang, Chua-Chin Wang
2008	J	`jnl`	Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection. J. Signal Process. Syst. Chua-Chin Wang, Gang-Neng Sung, Pai-Li Liu
2008	C	`conf`	Power-saving nano-scale DRAMs with an adaptive refreshing clock generator. ISCAS Tung-Han Tsai, Chin-Lin Chen, Ching-Li Lee, Chua-Chin Wang
2008	J	`jnl`	ZigBee 868/915-MHz Modulator/Demodulator for Wireless Personal Area Network. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Chi-Chun Huang, Jian-Ming Huang, Chih-Yi Chang, Chih-Peng Li
2007	J	`jnl`	A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Chua-Chin Wang, Ching-Li Lee, Wun-Ji Lin
2007	C	`conf`	A Low-power Sensorless Inverter Controller of Brushless DC Motors. ISCAS Chua-Chin Wang, Gang-Neng Sung, Kuan-Wen Fang, Sheng-Lun Tseng
2007	J	`jnl`	An 80MHz PLL with 72.7ps peak-to-peak jitter. Microelectron. J. Chua-Chin Wang, Gang-Neng Sung, Jian-Ming Huang, Li-Ping Lin
2007	C	`conf`	An Implantable Long-term Bladder Urine Pressure Measurement System with a 1-atm Canceling Instrumentation Amplifier. ISCAS Chua-Chin Wang, Chi-Chun Huang, Jian-Sing Liou, Yan-Jhin Ciou, I-Yu Huang, Chih-Peng Li, Yung-Chin Lee, Wen-Jen Wu
2007	J	`jnl`	Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator. Microelectron. J. Chua-Chin Wang, Tzung-Je Lee, Chih-Chen Li, Ron Hu
2006	—	`conf`	A 140-dB CMRR Low-noise Instrumentation Amplifier for Neural Signal Sensing. APCCAS Chua-Chin Wang, Chi-Chun Huang, Jian-Sing Liou, Kuan-Wen Fang
2006	C	`conf`	A 4-Kb low power 4-T SRAM design with negative word-line gate drive. ISCAS Chua-Chin Wang, Ching-Li Lee, Wun-Ji Lin
2006	C	`conf`	A 6.57 mW ZigBee transceiver for 868/915 MHz band. ISCAS Chua-Chin Wang, Jian-Ming Huang, Chih-Yi Chang, Kuang-Ting Cheng, Chih-Peng Li
2006	—	`conf`	A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR. APCCAS Chua-Chin Wang, Chi-Chun Huang, Tzung-Je Lee, U. Fat Chio
2006	—	`conf`	A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology. ISVLSI Chua-Chin Wang, Gang-Neng Sung
2006	—	`conf`	A Low-power 4-T SAM Design for OFDM Demodulators in DVB Receiversers. APCCAS Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ching-Li Lee, Cheng-Mu Wu, Ju-Ya Chen
2006	—	`conf`	An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V Sensitivity. APCCAS Chua-Chin Wang, Tzung-Je Lee, Chih-Chen Li, Ron Hu
2006	J	`jnl`	An All-MOS High-Linearity Voltage-to-Frequency Converter Chip With 520-kHz/V Sensitivity. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Tzung-Je Lee, Chih-Chen Li, Ron Hu
2006	—	`conf`	An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording. APCCAS Chua-Chin Wang, Chi-Chun Huang, Tzung-Je Lee, Cheng-Mu Wu, Gang-Neng Sung, Kuan-Wen Fang, Sheng-Lun Tseng, Jia-Jin Chen
2006	J	`jnl`	Clock-and-Data Recovery Design for LVDS Transceiver Used in LCD Panels. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Ching-Li Lee, Chun-Yang Hsiao, Jin-Fon Huang
2006	—	`conf`	Codec Design for Variable-Length to Fixed-Length Data Conversion for H.263. IIH-MSP Chua-Chin Wang, Gang-Neng Sung, Jia-Hao Li
2006	—	`conf`	Engery-Efficient Double-Edge Triggered Flip-Flop Design. APCCAS Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen
2006	J	`jnl`	High-sensitivity and high-mobility compact DVB-T receiver for in-car entertainment. IEEE Trans. Consumer Electron. Chua-Chin Wang, Tzung-Je Lee, Hoi Kam Lo, Shih-Ping Lin, Ron Hu
2006	J	`jnl`	Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Jian-Ming Huang, Yih-Long Tseng, Wun-Ji Lin, Ron Hu
2005	J	`jnl`	A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers. IEEE Trans. Consumer Electron. Chua-Chin Wang, Jian-Ming Huang, Hsian-Chang Cheng
2005	J	`jnl`	A multiparameter implantable microstimulator SOC. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Tzung-Je Lee, Yu-Tzu Hsiao, U. Fat Chio, Chi-Chun Huang, J.-J. J. Chin, Ya-Hsin Hsueh
2005	J	`jnl`	A temperature-insensitive self-recharging circuitry used in DRAMs. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Yih-Long Tseng, Chih-Chiang Chiu
2005	J	`jnl`	Low-Power Small-Area Digital I/O Cell. IEEE Trans. Circuits Syst. II Express Briefs Chua-Chin Wang, Ching-Li Lee, Yih-Long Tseng, Chiuan-Shian Chen, Ron Hu
2005	J	`jnl`	Low-cost video decoder with 2D2L comb filter for NTSC digital TVs. IEEE Trans. Consumer Electron. Chua-Chin Wang, Ching-Li Lee, Ming-Kai Chang
2005	J	`jnl`	Switched-current 3-bit CMOS 4.0-MHz wideband random signal generator. IEEE J. Solid State Circuits Chua-Chin Wang, Jian-Ming Huang, Hon-Chen Cheng, Ron Hu
2005	—	`conf`	Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC. ISCAS (1) Chua-Chin Wang, Ching-Li Lee, Li-Ping Lin, Yih-Long Tseng
2004	J	`jnl`	A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Ron Hu
2004	J	`jnl`	A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Chih-Chen Li, Ron Hu
2004	J	`jnl`	A 4-kB 500-MHz 4-T CMOS SRAM using low-V IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Yih-Long Tseng, Hon-Yuan Leo, Ron Hu
2004	—	`conf`	A C-less ASK demodulator for implantable neural interfacing chips. ISCAS (4) Chua-Chin Wang, Ya-Hsin Hsueh, U. Fat Chio, Yu-Tzu Hsiao
2004	—	`conf`	A phase-adjustable negative phase shifter using a single-shot locking method. ISCAS (2) Chua-Chin Wang, Ya-Hsin Hsueh, Sen-Fu Hong, Rong-Sui Kao
2004	—	`conf`	High-PSR bias circuitry for NTSC sync separation. ISCAS (1) Chua-Chin Wang, Yih-Long Tseng, Tzung-Je Lee, Ron Hu
2003	—	`conf`	A boosted wordline voltage generator for low-voltage memories. ICECS Chua-Chin Wang, Ya-Hsin Hsueh, Ting-Wan Kuo, Ron Hu
2003	J	`jnl`	An SRAM design using dual threshold voltage transistors and low-power quenchers. IEEE J. Solid State Circuits Chua-Chin Wang, Po-Ming Lee, Kuo-Long Chen
2003	J	`jnl`	An area-saving decoder structure for ROMs. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Ya-Hsin Hsueh, Ying-Pei Chen
2003	J	`jnl`	Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm. IEEE Trans. Very Large Scale Integr. Syst. Chua-Chin Wang, Po-Ming Lee, Jun-Jie Wang, Chenn-Jung Huang
2003	—	`conf`	Dual-polarity high voltage generator design for non-volatile memories. ICECS Chua-Chin Wang, Yih-Long Tseng, Tian-Hau Chen, Ron Hu
2002	—	`conf`	6-T SRAM using dual threshold voltage transistors and low-power quenchers. ICECS Chua-Chin Wang, Po-Ming Lee, Kuo-Long Chen
2002	—	`conf`	A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications. ICECS Chua-Chin Wang, Hsien-Chih She, Ron Hu
2002	J	`jnl`	A Fast Dynamic 64-bit Comparator with Small Transistor Count. VLSI Design Chua-Chin Wang, Ya-Hsin Hsueh, Hsin-Long Wu, Chih-Feng Wu
2002	—	`conf`	A ROM-less direct digital frequency synthesizer by using trigonometric quadruple angle formula. ICECS Chua-Chin Wang, Hsien-Chih She, Ron Hu
2002	J	`jnl`	A low-cost plasma display panel data dispatcher for image enhancement. IEEE Trans. Consumer Electron. Chua-Chin Wang, Ya-Hsin Hsueh, Chiuan-Shian Chen, Jih-Fon Huang
2002	J	`jnl`	An Embedded Low Transistor Count 8-bit Analog-to-digital Converter Using a Binary Searching Method. VLSI Design Chua-Chin Wang, Ya-Hsin Hsueh, Shao-Ku Huang
2002	J	`jnl`	Design of an Inter-plane Circuit for Clocked PLAs. VLSI Design Chua-Chin Wang, Ya-Hsin Hsueh, Yu-Tsun Chien, Ying-Pei Chen
2002	J	`jnl`	Image Processing Techniques for Wafer Defect Cluster Identification. IEEE Des. Test Comput. Chenn-Jung Huang, Chua-Chin Wang, Chi-Feng Wu
2002	J	`jnl`	Improved Design of C2PL 3-2 Compressors for Inner Product Processing. VLSI Design Chua-Chin Wang, Po-Ming Lee, Chenn-Jung Huang
2001	—	`conf`	A 1.0 GHz clock generator design with a negative delay using a single-shot locking method. ICECS Chua-Chin Wang, Yih-Long Tseng, Rong-Sui Kao
2001	—	`conf`	A 1.25 GHz 32-bit tree-structured carry lookahead adder. ISCAS (4) Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang
2001	J	`jnl`	A ratioed channel assignment scheme for initial and handoff calls in mobile cellular systems. Comput. Commun. Chenn-Jung Huang, Wei Kuang Lai, Chua-Chin Wang, Yu-Jyr Jin, Hsin Wei Chen
2001	—	`conf`	An area-saving 3-dimensional decoder structure for ROMs. ICECS Chua-Chin Wang, Ya-Hsin Hsueh, Ying-Pei Chen
2001	—	`conf`	Design of a cycle-efficient 64b/32b integer divider using a table-sharing method. ICECS Chua-Chin Wang, Po-Ming Lee, Jun-Jie Wang, Chenn-Jung Huang
2001	—	`conf`	Fast half-swing inter-plane circuits for clocked NOR-NOR PLAs. ICECS Chua-Chin Wang, Chih-Chiang Chiu, Yu-Tsung Chien
2001	J	`jnl`	Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network. J. Inf. Sci. Eng. Chua-Chin Wang, Cheng-Fa Tsai, Yu-Tsun Chien
2000	—	`conf`	A Novel Neural Architecture with High Storage Capacity. IJCNN (5) Chua-Chin Wang, Cheng-Fa Tsai
2000	J	`jnl`	A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop. VLSI Design Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen
2000	J	`jnl`	A deterministic capacity-finding method for multi-valued exponential BAM. IEEE Trans. Syst. Man Cybern. Part A Chua-Chin Wang, Chenn-Jung Huang, Shiou-Ming Hwang
2000	C	`conf`	A fast dynamic 64-bit comparator with small transistor count. ISCAS Chua-Chin Wang, Hsin-Long Wu, Chih-Feng Wu
2000	J	`jnl`	Design and Analysis of Digital Ratioed Compressors for Inner Product Processing. VLSI Design Chua-Chin Wang, Chenn-Jung Huang, Po-Ming Lee
2000	J	`jnl`	Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library. VLSI Design Chua-Chin Wang, Chenn-Jung Huang, I-Yen Chang
2000	C	`conf`	Design of an inter-plane circuit for clocked PLAs. ISCAS Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen
2000	J	`jnl`	Fuzzy data processing using polynomial bidirectional hetero-associative network. Inf. Sci. Chua-Chin Wang, Cheng-Fa Tsai
2000	C	`conf`	Improved design of C ISCAS Chua-Chin Wang, Po-Ming Lee, Chenn-Jung Hunng
2000	J	`jnl`	Single-ended SRAM with high test coverage and short test time. IEEE J. Solid State Circuits Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia-Hsiung Kao
1999	—	`conf`	A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. ISCAS (2) Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen
1999	—	`conf`	Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology. ICECS Chua-Chin Wang, Sheng-Hua Chen, Shen-Fu Hsiao, Chuan-lin Wu
1999	—	`conf`	Theoretical expectation value of the capacity of fuzzy polynomial bidirectional hetero-correlator. ISCAS (5) Chua-Chin Wang, Cheng-Fa Tsai
1998	J	`jnl`	Data compression by the recursive algorithm of exponential bidirectional associative memory. IEEE Trans. Syst. Man Cybern. Part B Chua-Chin Wang, Chang-Rong Tsai
1998	B	`conf`	Fuzzy data recall using polynomial bidirectional hetero-correlator. SMC Chua-Chin Wang, Cheng-Fa Tsai
1998	J	`jnl`	The Majority Theorem of Centralized Multiple BAMs Networks. Inf. Sci. Chua-Chin Wang, Hon-Son Don
1997	J	`jnl`	Digital Design of Discrete Exponential Bidirectional Associative Memory. J. VLSI Signal Process. Chua-Chin Wang, Chih-Lwan Fan
1996	J	`jnl`	Capacity analysis of the asymptotically stable multi-valued exponential bidirectional associative memory. IEEE Trans. Syst. Man Cybern. Part B Chua-Chin Wang, Shiou-Ming Hwang, Jyh-Ping Lee
1996	J	`jnl`	Practical Capacity and Attraction Radix Analysis of Exponential Bidirectional Associative Memory. J. Inf. Sci. Eng. Chua-Chin Wang
1995	J	`jnl`	An analysis of high-capacity discrete exponential BAM. IEEE Trans. Neural Networks Chua-Chin Wang, Hon-Son Don
1995	C	`conf`	Analysis and Current-Mode Implementation of Asymptotically Stable Exponential Bidirectional Associative Memory. ISCAS Chua-Chin Wang, Jeng-Ming Wu
1995	—	`conf`	Digital design of discrete exponential bidirectional associative memory. ICNN Chua-Chin Wang, Chih-Lwan Fan
1995	—	`conf`	Realization of bidirectional associative memory using a pseudo-parallel searching approach. ICNN Chua-Chin Wang, In-Hau Horng
1995	J	`jnl`	The decision-making properties of discrete multiple exponential bidirectional associative memories. IEEE Trans. Neural Networks Chua-Chin Wang, Jyh-Ping Lee
1994	J	`jnl`	A Modified Measure for Fuzzy Subsethood. Inf. Sci. Chua-Chin Wang, Hon-Son Don
1994	J	`jnl`	A Polar Model for Evidential Reasoning. Inf. Sci. Chua-Chin Wang, Hon-Son Don
1994	J	`jnl`	A robust continuous model for evidential reasoning. J. Intell. Robotic Syst. Chua-Chin Wang, Hon-Son Don