Christopher Torng

32 papers A* 8C 1Misc 1Journal 16Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
Capstone: Power-Capped Pipelining for Coarse-Grained Reconfigurable Array Compilers.
CoRR
Sabrina Yarzada, Christopher Torng
2026 J jnl
Onyx: A 12-nm Programmable Accelerator for Dense and Sparse Applications.
IEEE J. Solid State Circuits
Kalhan Koul, Olivia Hsu, Yuchen Mei, Sai Gautham Ravipati, Maxwell Strange, Jackson Melchert, Alex Carsello, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Zhouhua Xie, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina
2026 J jnl
PowerFlow-DNN: Compiler-Directed Fine-Grained Power Orchestration for End-to-End Edge AI Inference.
CoRR
Paul Chen, Jeongeun Kim, Wenbo Zhu, Yuanhan Li, Shunyao Huang, Chenjie Weng, Christopher Torng
2025 J jnl
A Vertically Integrated Framework for Templatized Chip Design.
CoRR
Jeongeun Kim, Christopher Torng
2025 J jnl
Algorithm-Driven On-Chip Integration for High Density and Low Cost.
CoRR
Jeongeun Kim, Sabrina Yarzada, Paul Chen, Christopher Torng
2024 J jnl
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
IEEE J. Solid State Circuits
Kathleen Feng, Taeyoung Kong, Kalhan Koul, Jackson Melchert, Alex Carsello, Qiaoyi Liu, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary A. Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Christopher Torng, Mark Horowitz, Priyanka Raina
2024 — conf
Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications.
VLSI Technology and Circuits
Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina
2024 — conf
Onyx: A Programmable Accelerator for Sparse Tensor Algebra.
HCS
Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina
2023 J jnl
AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.
ACM Trans. Embed. Comput. Syst.
Kalhan Koul, Jackson Melchert, Kavya Sreedhar, Leonard Truong, Gedeon Nyengele, Keyi Zhang, Qiaoyi Liu, Jeff Setter, Po-Han Chen, Yuchen Mei, Maxwell Strange, Ross Daly, Caleb Donovick, Alex Carsello, Taeyoung Kong, Kathleen Feng, Dillon Huff, Ankita Nayak, Rajsekhar Setaluri, James Thomas, Nikhil Bhagdikar, David Durst, Zachary A. Myers, Nestan Tsiskaridze, Stephen Richardson, Rick Bahr, Kayvon Fatahalian, Pat Hanrahan, Clark W. Barrett, Mark Horowitz, Christopher Torng, Fredrik Kjolstad, Priyanka Raina
2023 Misc conf
Building First-Order Energy Modeling Intuition in Computer Architecture Lectures.
WCAE
Christopher Torng
2023 J jnl
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays.
IEEE Comput. Archit. Lett.
Jackson Melchert, Keyi Zhang, Yuchen Mei, Mark Horowitz, Christopher Torng, Priyanka Raina
2023 J jnl
Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays.
CoRR
Taeyoung Kong, Kalhan Koul, Priyanka Raina, Mark Horowitz, Christopher Torng
2023 J jnl
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains.
ACM Trans. Reconfigurable Technol. Syst.
Ankita Nayak, Keyi Zhang, Rajsekhar Setaluri, Alex Carsello, Makai Mann, Christopher Torng, Stephen Richardson, Rick Bahr, Pat Hanrahan, Mark Horowitz, Priyanka Raina
2022 J jnl
A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Kavya Sreedhar, Mark Horowitz, Christopher Torng
2022 — conf
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
VLSI Technology and Circuits
Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary A. Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina
2022 — conf
Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.
HCS
Kathleen Feng, Alex Carsello, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary A. Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina
2022 J jnl
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays.
CoRR
Jackson Melchert, Keyi Zhang, Yuchen Mei, Mark Horowitz, Christopher Torng, Priyanka Raina
2022 A* conf
mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited.
DAC
Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark Horowitz, Priyanka Raina, Christopher Torng
2021 J jnl
Enabling Reusable Physical Design Flows with Modular Flow Generators.
CoRR
Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark Horowitz, Priyanka Raina, Christopher Torng
2021 J jnl
Fast Extended GCD Calculation for Large Integers for Verifiable Delay Functions.
IACR Cryptol. ePrint Arch.
Kavya Sreedhar, Mark Horowitz, Christopher Torng
2021 A* conf
Ultra-Elastic CGRAs for Irregular Loop Specialization.
HPCA
Christopher Torng, Peitian Pan, Yanghui Ou, Cheng Tan, Christopher Batten
2020 A* conf
Creating an Agile Hardware Design Flow.
DAC
Rick Bahr, Clark W. Barrett, Nikhil Bhagdikar, Alex Carsello, Ross Daly, Caleb Donovick, David Durst, Kayvon Fatahalian, Kathleen Feng, Pat Hanrahan, Teguh Hofstee, Mark Horowitz, Dillon Huff, Fredrik Kjolstad, Taeyoung Kong, Qiaoyi Liu, Makai Mann, Jackson Melchert, Ankita Nayak, Aina Niemetz, Gedeon Nyengele, Priyanka Raina, Stephen Richardson, Rajsekhar Setaluri, Jeff Setter, Kavya Sreedhar, Maxwell Strange, James Thomas, Christopher Torng, Leonard Truong, Nestan Tsiskaridze, Keyi Zhang
2019 — conf
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
VLSI Circuits
Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski
2019 C conf
PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks.
ICCD
Cheng Tan, Yanghui Ou, Shunning Jiang, Peitian Pan, Christopher Torng, Shady Agwa, Christopher Batten
2018 A* conf
A modular digital VLSI flow for high-productivity SoC design.
DAC
Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer
2018 J jnl
Four Monolithically Integrated Switched-Capacitor DC-DC Converters With Dynamic Capacitance Sharing in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ivan Bukreyev, Christopher Torng, Waclaw Godycki, Christopher Batten, Alyssa B. Apsel
2018 J jnl
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
IEEE Micro
Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, Michael B. Taylor
2017 A* conf
Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs.
MICRO
Ji Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, Christopher Batten
2016 A* conf
Asymmetry-Aware Work-Stealing Runtimes.
ISCA
Christopher Torng, Moyang Wang, Christopher Batten
2016 — conf
Experiences using a novel Python-based hardware modeling framework for computer architecture test chips.
Hot Chips Symposium
Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, Christopher Batten
2014 A* conf
Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks.
MICRO
Waclaw Godycki, Christopher Torng, Ivan Bukreyev, Alyssa B. Apsel, Christopher Batten
2013 A* conf
Microarchitectural mechanisms to exploit value structure in SIMT architectures.
ISCA
Ji Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, Christopher Batten