Christopher T. Clarke

23 papers B 2C 3Misc 1Journal 10Unranked 7
YearRankTypeTitle / Venue / Authors
2020 J jnl
An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array-System on Chip Technology.
ACM Trans. Reconfigurable Technol. Syst.
Alexander E. Beasley, Christopher T. Clarke, Robert J. Watson
2019 J jnl
Efficient digital implementation of a multi-precision square-root algorithm.
IET Comput. Digit. Tech.
Alexander E. Beasley, Robert J. Watson, Christopher T. Clarke
2018 J jnl
Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design.
IEEE Trans. Very Large Scale Integr. Syst.
Alok Prakash, Christopher T. Clarke, Siew-Kei Lam, Thambipillai Srikanthan
2014 J jnl
Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst.
Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan
2014 J jnl
Improved Signal Processing Methods for Velocity Selective Neural Recording Using Multi-Electrode Cuffs.
IEEE Trans. Biomed. Circuits Syst.
Assad I. Al-Shueli, Christopher T. Clarke, Nick Donaldson, John Taylor
2014 J jnl
Rapid evaluation of custom instruction selection approaches with FPGA estimation.
ACM Trans. Embed. Comput. Syst.
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
2013 J jnl
FPGA-aware techniques for rapid generation of profitable custom instructions.
Microprocess. Microsystems
Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan
2013 — conf
Modelling communication overhead for accessing local memories in hardware accelerators.
ASAP
Alok Prakash, Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
2012 B conf
Custom instructions with local memory elements without expensive DMA transfers.
FPL
Alok Prakash, Christopher T. Clarke, Thambipillai Srikanthan
2012 B conf
Examination of the concept of a row-column separated median filter.
FPL
Di Wang, Christopher T. Clarke, A. N. Evans
2012 — conf
Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration.
ReCoSoC
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
2011 J jnl
Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs.
IEEE Trans. Computers
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
2011 — conf
Instruction set customization for area-constrained FPGA designs.
SoCC
Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan
2009 J jnl
Selecting Profitable Custom Instructions for Area-Time-Efficient Realization on Reconfigurable Architectures.
IEEE Trans. Ind. Electron.
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
2008 C conf
Analogue/digital interface and communications aspects in a multi-channel ENG recording asic.
ISCAS
Christopher T. Clarke, John Taylor, Xianhong Xu
2007 — conf
Real Time Tracking of Camera Motion Through Cylindrical Passages.
DSP
Suchitra Sathyanarayana, Srikanthan Thambipillai, Christopher T. Clarke
2006 — conf
Profile Directed Instruction Cache Tuning for Embedded Systems.
ISVLSI
Kugan Vivekanandarajah, Thambipillai Srikanthan, Christopher T. Clarke
2006 J jnl
Rapid generation of custom instructions using predefined dataflow structures.
Microprocess. Microsystems
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
2005 — conf
Elimination of sign precomputation in flat CORDIC.
ISCAS (4)
Suchitra Sathyanarayana, S. Sukthankar, Thambipillai Srikanthan, Christopher T. Clarke
2003 — conf
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design.
Embedded Systems and Applications
Kugan Vivekanandarajah, Thambipillai Srikanthan, Christopher T. Clarke, Saurav Bhattacharyya
1999 C conf
A Reverse Converter for the 4-moduli Superset {2
IEEE Symposium on Computer Arithmetic
Manish Bhardwaj, Thambipillai Srikanthan, Christopher T. Clarke
1999 C conf
VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion Perspectiv.
IEEE Symposium on Computer Arithmetic
Manish Bhardwaj, Thambipillai Srikanthan, Christopher T. Clarke
1998 Misc conf
Designing efficient residue arithmetic based VLSI correlators.
ICASSP
Aniruddha A. Deodhar, Manish Bhardwaj, Christopher T. Clarke, Thambipillai Srikanthan