Christopher J. Hughes

50 papers A* 21A 9B 5Misc 1Journal 10Unranked 2

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	AccelFlow: Orchestrating an On-Package Ensemble of Fine-Grained Accelerators for Microservices. HPCA Jovan Stojkovic, Abraham Farrell, Zhangxiaowen Gong, Christopher J. Hughes, Josep Torrellas
2025	—	`conf`	FlexInfer: Flexible LLM Inference with CPU Computations. MLSys Seonjin Na, Geonhwa Jeong, Byung Hoon Ahn, Aaron Jezghani, Jeffrey Young, Christopher J. Hughes, Tushar Krishna, Hyesoon Kim
2025	A*	`conf`	Push Multicast: A Speculative and Coherent Interconnect for Mitigating Manycore CPU Communication Bottleneck. HPCA Jiayi Huang, Yanhua Chen, Zhe Wang, Christopher J. Hughes, Yufei Ding, Yuan Xie
2025	A*	`conf`	Software Prefetch Multicast: Sharer-Exposed Prefetching for Bandwidth Efficiency in Manycore Processors. MICRO Yanhua Chen, Jiong Feng, Zhe Wang, Christopher J. Hughes, Jiayi Huang
2024	A	`conf`	M3XU: Achieving High-Precision and Complex Matrix Multiplication with Low-Precision MXUs. SC Dongho Ha, Yunan Zhang, Chen-Chien Kao, Christopher J. Hughes, Won Woo Ro, Hung-Wei Tseng
2023	A*	`conf`	VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs. HPCA Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya, Eric Qin, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna
2023	J	`jnl`	VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs. CoRR Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya, Eric Qin, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna
2022	A*	`conf`	Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques. ISCA Zhangxiaowen Gong, Houxiang Ji, Yao Yao, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas
2021	A*	`conf`	RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. DAC Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna
2021	J	`jnl`	RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. CoRR Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna
2021	A	`conf`	SumMerge: an efficient algorithm and implementation for weight repetition-aware DNN inference. ICS Rohan Baskar Prabhakar, Sachit Kuhar, Rohit Agrawal, Christopher J. Hughes, Christopher W. Fletcher
2020	A*	`conf`	SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs. MICRO Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Sara S. Baghsorkhi, Josep Torrellas
2020	B	`conf`	SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors. PACT Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas
2020	A	`conf`	SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey
2019	B	`conf`	Forgive-TM: Supporting Lazy Conflict Detection In Eager Hardware Transactional Memory. PACT Sunjae Park, Christopher J. Hughes, Milos Prvulovic
2019	J	`jnl`	SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors. CoRR Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas
2019	Misc	`conf`	T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations. FCCM Nitish Kumar Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang, David H. Albonesi, Vivek Sarkar, Wenguang Chen, Paul Petersen, Geoff Lowney, Adam Herr, Christopher J. Hughes, Timothy G. Mattson, Pradeep Dubey
2018	—	`conf`	Dynamic fine-grained sparse memory accesses. MEMSYS Berkin Akin, Chiachen Chou, Jongsoo Park, Christopher J. Hughes, Rajat Agarwal
2018	B	`conf`	Transactional pre-abort handlers in hardware transactional memory. PACT Sunjae Park, Christopher J. Hughes, Milos Prvulovic
2017	J	`jnl`	Banshee: Bandwidth-Efficient DRAM Caching Via Software/Hardware Cooperation. CoRR Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, Onur Mutlu, Srinivas Devadas
2017	A*	`conf`	Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation. MICRO Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, Onur Mutlu, Srinivas Devadas
2016	A*	`conf`	PleaseTM: Enabling transaction conflict management in requester-wins hardware transactional memory. HPCA Sunjae Park, Milos Prvulovic, Christopher J. Hughes
2015	A*	`conf`	IMP: indirect memory prefetcher. MICRO Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, Srinivas Devadas
2015	—	`book`	Single-Instruction Multiple-Data Execution Christopher J. Hughes
2013	A	`conf`	Exploring SIMD for Molecular Dynamics, Using Intel® Xeon® Processors and Intel® Xeon Phi Coprocessors. IPDPS Simon J. Pennycook, Christopher J. Hughes, Mikhail Smelyanskiy, Stephen A. Jarvis
2013	B	`conf`	Locality-aware task management for unstructured parallelism: a quantitative limit study. SPAA Richard M. Yoo, Christopher J. Hughes, Changkyu Kim, Yen-Kuang Chen, Christos Kozyrakis
2013	A	`conf`	Location-aware cache management for many-core processors with deep cache hierarchy. SC Jongsoo Park, Richard M. Yoo, Daya Shanker Khudia, Christopher J. Hughes, Daehyun Kim
2013	A	`conf`	Performance evaluation of Intel® transactional synchronization extensions for high-performance computing. SC Richard M. Yoo, Christopher J. Hughes, Konrad Lai, Ravi Rajwar
2011	J	`jnl`	DeFT: Design space exploration for on-the-fly detection of coherence misses. ACM Trans. Archit. Code Optim. Guru Venkataramani, Christopher J. Hughes, Sanjeev Kumar, Milos Prvulovic
2011	A*	`conf`	LIME: a framework for debugging load imbalance in multi-threaded execution. ICSE Jungju Oh, Christopher J. Hughes, Guru Venkataramani, Milos Prvulovic
2011	A*	`conf`	Moguls: a model to explore the memory hierarchy for bandwidth improvements. ISCA Guangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen
2010	J	`jnl`	Performance and Energy Implications of Many-Core Caches for Throughput Computing. IEEE Micro Christopher J. Hughes, Changkyu Kim, Yen-Kuang Chen
2009	J	`jnl`	Parallel scalability in speech recognition. IEEE Signal Process. Mag. Kisun You, Jike Chong, Youngmin Yi, Ekaterina Gonina, Christopher J. Hughes, Yen-Kuang Chen, Wonyong Sung, Kurt Keutzer
2009	A	`conf`	Scalable HMM based inference engine in large vocabulary continuous speech recognition. ICME Jike Chong, Kisun You, Youngmin Yi, Ekaterina Gonina, Christopher J. Hughes, Wonyong Sung, Kurt Keutzer
2008	A*	`conf`	Atomic Vector Operations on Chip Multiprocessors. ISCA Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Yen-Kuang Chen, Jatin Chhugani, Christopher J. Hughes, Changkyu Kim, Victor W. Lee, Anthony D. Nguyen
2008	J	`jnl`	Convergence of Recognition, Mining, and Synthesis Workloads and Its Implications. Proc. IEEE Yen-Kuang Chen, Jatin Chhugani, Pradeep Dubey, Christopher J. Hughes, Daehyun Kim, Sanjeev Kumar, Victor W. Lee, Anthony D. Nguyen, Mikhail Smelyanskiy
2007	A*	`conf`	Carbon: architectural support for fine-grained parallelism on chip multiprocessors. ISCA Sanjeev Kumar, Christopher J. Hughes, Anthony D. Nguyen
2007	A	`conf`	Computer Vision on Multi-Core Processors: Articulated Body Tracking. ICME Trista Pei-Chun Chen, Dmitry Budnikov, Christopher J. Hughes, Yen-Kuang Chen
2007	A*	`conf`	Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors. ISCA Christopher J. Hughes, Radek Grzeszczuk, Eftychios Sifakis, Daehyun Kim, Sanjeev Kumar, Andrew Selle, Jatin Chhugani, Matthew J. Holliman, Yen-Kuang Chen
2006	B	`conf`	Hybrid transactional memory. PPoPP Sanjeev Kumar, Michael Chu, Christopher J. Hughes, Partha Kundu, Anthony D. Nguyen
2006	A*	`conf`	Incremental approximate matrix factorization for speeding up support vector machines. KDD Gang Wu, Edward Y. Chang, Yen-Kuang Chen, Christopher J. Hughes
2005	J	`jnl`	Memory-side prefetching for linked data structures for processor-in-memory systems. J. Parallel Distributed Comput. Christopher J. Hughes, Sarita V. Adve
2004	A*	`conf`	A Formal Approach to Frequent Energy Adaptations for Multimedia Applications. ISCA Christopher J. Hughes, Sarita V. Adve
2003	—	`—`	General -Purpose Processors for Multimedia Applications: Predictability and Energy Efficiency Christopher J. Hughes
2002	A*	`conf`	Joint local and global hardware adaptations for energy. ASPLOS Ruchira Sasanka, Christopher J. Hughes, Sarita V. Adve
2002	J	`jnl`	RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors. Computer Christopher J. Hughes, Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve
2002	A	`conf`	Soft Real- Time Scheduling on Simultaneous Multithreaded Processors. RTSS Rohit Jain, Christopher J. Hughes, Sarita V. Adve
2001	A*	`conf`	Saving energy with architectural and frequency adaptations for multimedia applications. MICRO Christopher J. Hughes, Jayanth Srinivasan, Sarita V. Adve
2001	A*	`conf`	Speculative precomputation: long-range prefetching of delinquent loads. ISCA Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen
2001	A*	`conf`	Variability in the execution of multimedia applications and implications for architecture. ISCA Christopher J. Hughes, Praful Kaul, Sarita V. Adve, Rohit Jain, Chanik Park, Jayanth Srinivasan