Christian Landrault

92 papers A* 1A 13B 4C 6Misc 14Journal 24Unranked 30

Year	Rank	Type	Title / Venue / Authors
2009	J	`jnl`	A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. J. Electron. Test. Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2009	J	`jnl`	Is triple modular redundancy suitable for yield improvement? IET Comput. Digit. Tech. Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2009	B	`conf`	Something I Always Wanted to Know About Test, But Was Afraid to Ask. ETS Christian Landrault
2008	J	`jnl`	A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electron. Test. Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
2008	—	`conf`	Improving Diagnosis Resolution without Physical Information. DELTA Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	A	`conf`	SoC Yield Improvement: Redundant Architectures to the Rescue? ITC Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	—	`conf`	Using TMR Architectures for Yield Improvement. DFT Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	C	`conf`	Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	C	`conf`	A Mixed Approach for Unified Logic Diagnosis. DDECS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	A	`conf`	A concurrent approach for testing address decoder faults in eFlash memories. ITC Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga
2007	B	`conf`	DERRIC: A Tool for Unified Logic Diagnosis. ETS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	B	`conf`	Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. ETS Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	J	`jnl`	Editorial. IET Comput. Digit. Tech. Christian Landrault, Erik Jan Marinissen
2007	B	`conf`	Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. ETS Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	—	`conf`	Fast Bridging Fault Diagnosis using Logic Information. ATS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	—	`conf`	Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. ATS Magali Bastian, Vincent Gouin, Patrick Girard, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel
2007	Misc	`conf`	Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	A	`conf`	Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	Misc	`conf`	Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2006	J	`jnl`	A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2006	Misc	`conf`	An Overview of Failure Mechanisms in Embedded Flash Memories. VTS Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2006	—	`conf`	Power-Aware Test Data Compression for Embedded IP Cores. ATS Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Serge Pravossoudovitch, Christian Landrault
2006	C	`conf`	Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
2005	—	`conf`	Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
2005	C	`conf`	Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault
2004	A	`conf`	Design of Routing-Constrained Low Power Scan Chains. DATE Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004	—	`conf`	Design of Routing-Constrained Low Power Scan Chains. DELTA Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004	J	`jnl`	Power-Driven Routing-Constrained Scan Chain Design. J. Electron. Test. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2003	J	`jnl`	A Ring Architecture Strategy for BIST Test Pattern Generation. J. Electron. Test. Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault
2003	J	`jnl`	A Unified DFT Approach for BIST and External Test. J. Electron. Test. Marie-Lise Flottes, Christian Landrault, A. Petitqueux
2003	A	`conf`	Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2003	J	`jnl`	Guest Editorial. J. Electron. Test. Christian Landrault
2002	J	`jnl`	Guest Editorial. J. Electron. Test. Christian Landrault
2002	J	`jnl`	Hardware Generation of Random Single Input Change Test Sequences. J. Electron. Test. René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2002	J	`jnl`	High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Des. Test Comput. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich
2002	Misc	`conf`	On Using Efficient Test Sequences for BIST. VTS René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2002	A	`conf`	Power Driven Chaining of Flip-Flops in Scan Architectures. ITC Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2002	—	`conf`	Test Power: a Big Issue in Large SOC Designs. DELTA Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2001	—	`conf`	A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2001	—	`conf`	A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2001	Misc	`conf`	A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2001	J	`jnl`	Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. J. Electron. Test. Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2001	C	`conf`	Interconnect Capacitance Modelling in a VDSM CMOS Technology. VLSI-SOC David Bernard, Christian Landrault, Pascal Nouet
2001	—	`conf`	On hardware generation of random single input change test sequences. ETW René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2001	C	`conf`	Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2000	—	`conf`	An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2000	—	`conf`	Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2000	—	`conf`	Delay fault testing: choosing between random SIC and random MIC test sequences. ETW Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2000	—	`conf`	Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. Asian Test Symposium Marie-Lise Flottes, Christian Landrault, A. Petitqueux
2000	J	`jnl`	Guest Editorial. J. Electron. Test. Christian Landrault
2000	Misc	`conf`	Hidden Markov and Independence Models with Patterns for Sequential BIST. VTS Laurent Bréhélin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault
2000	J	`jnl`	Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
2000	A	`conf`	Low power BIST design by hypergraph partitioning: methodology and architectures. ITC Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch
1999	J	`jnl`	A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. J. Electron. Test. Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
1999	Misc	`conf`	A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
1999	—	`conf`	A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
1999	—	`conf`	Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
1999	A	`conf`	Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts. DATE A. Toulouse, David Bernard, Christian Landrault, Pascal Nouet
1999	J	`jnl`	Guest Editorial. J. Electron. Test. Christian Landrault
1999	—	`conf`	Low power BIST by filtering non-detecting vectors. ETW Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
1999	—	`conf`	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos
1999	—	`conf`	On calculating efficient LFSR seeds for built-in self test. ETW Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault
1999	—	`conf`	Partial set for flip-flops based on state requirement for non-scan BIST scheme. ETW Marie-Lise Flottes, Christian Landrault, A. Petitqueux
1998	—	`conf`	A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
1998	—	`conf`	A Ring Architecture Strategy for BIST Test Pattern Generation. Asian Test Symposium Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault
1997	A	`conf`	A gate resizing technique for high reduction in power consumption. ISLPED Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
1997	J	`jnl`	A non-iterative gate resizing algorithm for high reduction in power consumption. Integr. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
1997	Misc	`conf`	An optimized BIST test pattern generator for delay testing. VTS Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch
1997	—	`conf`	Automatic Testability Analysis of Boards and MCMs at Chip Level. Asian Test Symposium Marc Perbost, Ludovic Le Lan, Christian Landrault
1997	Misc	`conf`	Hardware Test: Can We Learn from Software Testing? VTS J. Abraham, Phyllis G. Frankl, Christian Landrault, Meryem Marzouki, Paolo Prinetto, Chantal Robach, Pascale Thévenod-Fosse
1997	A	`conf`	On Using Machine Learning for Logic BIST. ITC Christophe Fagot, Patrick Girard, Christian Landrault
1996	A	`conf`	A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. ITC Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
1996	Misc	`conf`	A new test pattern generation method for delay fault testing. VTS S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1996	—	`conf`	DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. ED&TC P. Cavallera, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1995	—	`conf`	A trace-based method for delay fault diagnosis in synchronous sequential circuits. ED&TC Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
1995	J	`jnl`	An advanced diagnostic method for delay faults in combinational faulty circuits. J. Electron. Test. Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1995	J	`jnl`	Delay fault diagnosis in sequential circuits based on path tracing. Integr. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
1995	Misc	`conf`	Diagnostic of path and gate delay faults in non-scan sequential circuits. VTS Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
1995	A	`conf`	Is High-Level Test Synthesis Just Design for Test? ITC Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre
1995	—	`conf`	Test configurations to enhance the testability of sequential circuits. Asian Test Symposium S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault
1994	—	`conf`	Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. EDAC-ETC-EUROASIC D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1993	A	`conf`	An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. ITC D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1992	Misc	`conf`	A New Reliable Method for Delay-Fault Diagnosis. VLSI Design Marie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1992	A*	`conf`	A Novel Approach to Delay-Fault Diagnosis. DAC Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1992	Misc	`conf`	BIST linear generator based on complemented outputs. VTS Lew Fock Chong Lew Yan Voon, Christian Dufaza, Christian Landrault
1992	J	`jnl`	Delay-Fault Diagnosis by Critical-Path Tracing. IEEE Des. Test Comput. Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1992	Misc	`conf`	Quasi-Linear FSMS and their Application to the Generation of Deterministic and Pseudo-random Test Vectors. VLSI Design Lew Fock Chong Lew Yan Voon, Christian Dufaza, Christian Landrault
1991	J	`jnl`	Fault modeling and fault equivalence in CMOS technology. J. Electron. Test. Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch
1990	—	`conf`	Fault modelling and fault equivalence in CMOS technology. EURO-DAC Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch
1980	J	`jnl`	Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor. IEEE Trans. Computers Yves Crouzet, Christian Landrault
1978	J	`jnl`	Reliability and Availability Models for Maintained Systems Featuring Hardware Failures and Design Faults. IEEE Trans. Computers Alain Costes, Christian Landrault, Jean-Claude Laprie
1978	—	`conf`	SURF - A Program for Modeling and Reliability Prediction for Fault-Tolerant Computing Systems. Jerusalem Conference on Information Technology Christian Landrault, Jean-Claude Laprie