Chris R. Jesshope

95 papers A* 1A 4B 2C 8Misc 4Journal 35Unranked 38
YearRankTypeTitle / Venue / Authors
2014 A conf
A fault detection mechanism in a Data-flow scheduled Multithreaded processor.
DATE
Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang
2014 C conf
Analytical-Based High-Level Simulation of the Microthreaded Many-Core Architectures.
PDP
Muhammad Irfan Uddin, Raphael Poss, Chris R. Jesshope
2014 J jnl
Cache-based high-level simulation of microthreaded many-core architectures.
J. Syst. Archit.
Muhammad Irfan Uddin, Raphael Poss, Chris R. Jesshope
2014 J jnl
On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches.
ACM Trans. Embed. Comput. Syst.
Qiang Yang, Jian Fu, Raphael Poss, Chris R. Jesshope
2014 B conf
Rethread: A Low-Cost Transient Fault Recovery Scheme for Multithreaded Processors.
ARES
Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang
2014 C conf
Signature-based high-level simulation of microthreaded many-core architectures.
SIMULTECH
Muhammad Irfan Uddin, Raphael Poss, Chris R. Jesshope
2013 J jnl
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management.
Microprocess. Microsystems
Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Muhammad Irfan Uddin, Chris R. Jesshope
2013 — conf
MGSim - A simulation environment for multi-core research and education.
ICSAMOS
Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Muhammad Irfan Uddin, Chris R. Jesshope
2013 J jnl
MGSim - Simulation tools for multi-core processor architectures
CoRR
Mike Lankamp, Raphael 'kena' Poss, Qiang Yang, Jian Fu, Muhammad Irfan Uddin, Chris R. Jesshope
2013 — conf
On-demand thread-level fault detection in a concurrent programming environment.
ICSAMOS
Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang
2012 C conf
Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management.
DSD
Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Chris R. Jesshope
2012 — conf
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores.
RAPIDO
Muhammad Irfan Uddin, Chris R. Jesshope, Michiel W. van Tol, Raphael Poss
2011 — conf
A Micro Threading Based Concurrency Model for Parallel Computing.
IPDPS Workshops
Qiang Yang, Chris R. Jesshope, Jian Fu
2011 — conf
Efficient Memory Copy Operations on the 48-core Intel SCC Processor.
MARC Symposium
Michiel W. van Tol, Roy Bakker, Merijn Verstraaten, Clemens Grelck, Chris R. Jesshope
2011 — conf
Engineering Concurrent Software Guided by Statistical Performance Analysis.
PARCO
Clemens Grelck, Kevin Hammond, Heinz Hertlein, Philip K. F. Hölzenspies, Chris R. Jesshope, Raimund Kirner, Bernd Scheuermann, Alexander V. Shafarenko, Iraneus te Boekhorst, Volkmar Wieser
2011 J jnl
High Level Simulation of SVP Many-Core Systems.
Parallel Process. Lett.
Muhammad Irfan Uddin, Michiel W. van Tol, Chris R. Jesshope
2011 — conf
Mapping Distributed S-Net on the 48-core Intel SCC processor.
MARC Symposium
Merijn Verstraaten, Clemens Grelck, Michiel W. van Tol, Roy Bakker, Chris R. Jesshope
2010 Misc conf
An Operating System Strategy for General-purpose Parallel Computing on Many-core Architectures.
High Performance Computing Workshop
Michiel W. van Tol, Chris R. Jesshope
2010 J jnl
On the Compilation of a Language for General Concurrent Target Architectures.
Parallel Process. Lett.
Thomas A. M. Bernard, Clemens Grelck, Chris R. Jesshope
2010 — conf
Resource-Agnostic Programming for Many-Core Microgrids.
Euro-Par Workshops
Thomas A. M. Bernard, Clemens Grelck, Michael A. Hicks, Chris R. Jesshope, Raphael Poss
2010 — conf
Towards scalable I/O on a many-core architecture.
ICSAMOS
Michael A. Hicks, Michiel W. van Tol, Chris R. Jesshope
2009 J jnl
An implementation of the SANE Virtual Processor using POSIX threads.
J. Syst. Archit.
Michiel W. van Tol, Chris R. Jesshope, Mike Lankamp, Simon Polstra
2009 — conf
Evaluating CMPs and Their Memory Architecture.
ARCS
Chris R. Jesshope, Mike Lankamp, Li Zhang
2009 — conf
HPPC 2009 Panel: Are Many-Core Computer Vendors on Track?
Euro-Par Workshops
Martti Forsell, H. Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff
2009 J jnl
Implementation and evaluation of a microthread architecture.
J. Syst. Archit.
Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp
2009 — conf
Making multi-cores mainstream - from security to scalability.
PARCO
Chris R. Jesshope, Michael A. Hicks, Mike Lankamp, Raphael 'kena' Poss, Li Zhang
2009 J jnl
The implementation of an SVP many-core processor and the evaluation of its memory architecture.
SIGARCH Comput. Archit. News
Chris R. Jesshope, Mike Lankamp, Li Zhang
2008 — conf
A general model of concurrency and its implementation as many-core dynamic RISC processors.
ICSAMOS
Thomas A. M. Bernard, Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp, Michiel W. van Tol, Li Zhang
2008 — conf
An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency.
SAMOS
Chris R. Jesshope, Jean-Marc Philippe, Michiel W. van Tol
2008 — conf
Building a Concurrency and Resource Allocation Model into a Processor's ISA.
Euro-Par Workshops
Chris R. Jesshope
2008 A conf
Concurrency engineering.
ACSAC
Chris R. Jesshope, Alexander V. Shafarenko
2008 — conf
Introduction to Programming Multicores.
SAMOS
Chris R. Jesshope
2008 J jnl
Operating Systems in silicon and the Dynamic Management of Resources in Many-Core Chips.
Parallel Process. Lett.
Chris R. Jesshope
2008 — conf
The Verification of the On-Chip COMA Cache Coherence Protocol.
AMAST
Thuy Duong Vu, Li Zhang, Chris R. Jesshope
2007 J jnl
Asynchronous arbiter for micro-threaded chip multiprocessors.
J. Syst. Archit.
Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope
2007 C conf
Formalizing SANE Virtual Processor in Thread Algebra.
ICFEM
Thuy Duong Vu, Chris R. Jesshope
2007 C conf
High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids.
AICCSA
Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope
2007 C ed.
Network and Parallel Computing, IFIP International Conference, NPC 2007, Dalian, China, September 18-21, 2007, Proceedings
NPC
Keqiu Li, Chris R. Jesshope, Hai Jin, Jean-Luc Gaudiot
2007 — conf
On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores.
Euro-Par Workshops
Li Zhang, Chris R. Jesshope
2007 — conf
Strategies for Compiling µ TC to Novel Chip Multiprocessors.
SAMOS
Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg
2006 Misc conf
A Model for the Design and Programming of Multi-cores.
High Performance Computing Workshop
Chris R. Jesshope
2006 — ed.
Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings
Asia-Pacific Computer Systems Architecture Conference
Chris R. Jesshope, Colin Egan
2006 J jnl
Guest Editor's Introduction (Part 2).
Int. J. Parallel Program.
Chris R. Jesshope, Alexander V. Shafarenko
2006 J jnl
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors.
Comput. J.
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
2006 J jnl
Microthreading a Model for Distributed Instruction-level Concurrency.
Parallel Process. Lett.
Chris R. Jesshope
2006 — conf
Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors.
ARCS
Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope
2006 J jnl
Special issue on Micro-grids - Guest Editor Introduction.
Int. J. Parallel Program.
Chris R. Jesshope, Alexander V. Shafarenko
2006 J jnl
Supporting Microthread Scheduling and Synchronisation in CMPs.
Int. J. Parallel Program.
Ian M. Bell, Nabil Hasasneh, Chris R. Jesshope
2006 — conf
muTC - An Intermediate Language for Programming Chip Multiprocessors.
Asia-Pacific Computer Systems Architecture Conference
Chris R. Jesshope
2005 — conf
The Challenges of Massive On-Chip Concurrency.
Asia-Pacific Computer Systems Architecture Conference
Kostas Bousias, Chris R. Jesshope
2004 B conf
A General Learning Management System Based on Schema-driven Methodology.
ICALT
Lipeng Wen, Chris R. Jesshope
2004 Misc conf
Microgrids - The exploitation of massive on-chip concurrency.
High Performance Computing Workshop
Chris R. Jesshope
2004 — conf
Scalable Instruction-Level Parallelism..
SAMOS
Chris R. Jesshope
2003 — conf
Multi-threaded Microprocessors - Evolution or Revolution.
Asia-Pacific Computer Systems Architecture Conference
Chris R. Jesshope
2003 A conf
Web Services Technology and Learning Technology- A Web-Services Model for Constructing Decentralized Virtual Learning Environments.
ICWS
Lipeng Wen, Chris R. Jesshope
2001 — conf
Adaptivity in Web-based Educational System.
WWW Posters
Hong Hong, Neena Albi, Kinshuk, Xiaoqin He, Ashok Patel, Chris R. Jesshope
2001 J jnl
Cost-Effective Multimedia in On-line Teaching.
J. Educ. Technol. Soc.
Chris R. Jesshope
2001 A conf
Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines.
ACSAC
Chris R. Jesshope
2001 — conf
Technology Integrated Learning Environment - A Web-based Distance Learning System.
IMSA
Regina Gehne, Chris R. Jesshope, Zhenzi Zhang
2001 — conf
Topic 12: Routing and Communication in Interconnection Networks.
Euro-Par
Ramón Beivide, Chris R. Jesshope, Antonio Robles, Cruz Izu
2000 — conf
Micro-Threading: A New Approach to Future RISC.
ACAC
Chris R. Jesshope, Bing Luo
1999 J jnl
Computers as Tutors: Solving the Crisis in Education.
J. Educ. Technol. Soc.
Chris R. Jesshope
1999 — conf
Parallel Computer Architecture - What Is Its Future? Introduction.
Euro-Par
Chris R. Jesshope
1998 — conf
Multi-campus teaching using computer networks.
ACSE
Murray Pearson, Chris R. Jesshope
1997 J jnl
Optical Interconnectivity in a Scalable Data-Parallel System.
J. Parallel Distributed Comput.
Julian A. B. Dines, John F. Snowdon, Marc P. Y. Desmulliez, Dima B. Barsky, Alexander V. Shafarenko, Chris R. Jesshope
1997 — conf
Web based teaching: a minimalist approach.
ACSE
Chris R. Jesshope
1996 — conf
A FORTRAN 90 to F-code Compiler.
UK Parallel
Horia C. Slusanschi, Chris R. Jesshope
1996 Misc conf
Optical Interconnection hardware for scalable systems.
PDPTA
Julian A. B. Dines, John F. Snowdon, Marc P. Y. Desmulliez, D. T. Nielson, Dima B. Barsky, Alexander V. Shafarenko, Chris R. Jesshope
1996 — ed.
UK Parallel '96 - Proceedings of the BCS PPSG Annual Conference, Surrey, UK, July 3-5, 1996
UK Parallel
Chris R. Jesshope, Shasha Shafarenko
1995 J jnl
Multiprocessing: Trade-offs in computation and communication : Vijay K Naik Kluwer Academic Publishers, Dordrecht, The Netherlands (1993) ISBN 0 7923 9370 8, Dfl 180.00, £65.50, pp224.
Microprocess. Microsystems
Chris R. Jesshope
1995 — conf
Parallel Boltzmann Machine Topologies for Simulated Annealing Realisation of Combinatorial Problems.
ICANNGA
I. Ashman, T. Vladimirova, Chris R. Jesshope, R. Peel
1994 — conf
Asynchronous packet routers.
Interconnection Networks and Mapping and Scheduling Parallel Computations
Chris R. Jesshope, Ivailo M. Nedelchev
1994 — conf
Basic building blocks for asynchronous packet routers.
Great Lakes Symposium on VLSI
Ivailo M. Nedelchev, Chris R. Jesshope
1994 C conf
Mad-postman : A Look-ahead Message Propagation Method For Static Bidimensional Meshes.
PDP
Cruz Izu, Ramón Beivide, Chris R. Jesshope
1994 J jnl
Mechanized Reasoning and Hardware Design: C A R Hoare and M J C Gordon (Eds) Prentice Hall, Hemel Hempstead, UK (1992) ISBN 0 13 572405 8, £40, pp 151.
Microprocess. Microsystems
Chris R. Jesshope
1994 — ed.
Parcella 1994, VI. International Workshop on Parallel Processing by Cellular Automata and Arrays, Potsdam, Germany, September 21-23, 1994. Proceedings
Parcella
Chris R. Jesshope, Vesselin Jossifov, Wolfgang Wilhelmi
1993 J jnl
Experimental evaluation of Mad Postman bidimensional routing networks.
Microprocess. Microprogramming
Cruz Izu, Ramón Beivide, Chris R. Jesshope, Agustin Arruabarrena
1993 J jnl
Latency Reduction in VLSI Routers.
Parallel Process. Lett.
Chris R. Jesshope
1993 J jnl
The MP1 Network Chip and its Application to Parallel Computers.
Comput. J.
Chris R. Jesshope, Cruz Izu
1993 C conf
The MP1 network chip.
PDP
Chris R. Jesshope, Cruz Izu
1991 J jnl
Computing with parallel architectures: T.node: Gassilloud, D and Grossetie, J C (Eds) Kluwer (1991) pp 241, £52, ISBN 0792-31225-2.
Microprocess. Microsystems
Chris R. Jesshope
1991 — conf
Simulation Facility of Distributed Memory System with "Mad Postman" Communication Network.
EDMCC
Vladimir Getov, Chris R. Jesshope
1990 J jnl
Distributed computer systems: Zedan, H S M (Ed.) Butterworths, Borough Green, UK (1990) £48.00, pp 313.
Microprocess. Microsystems
Chris R. Jesshope
1989 J jnl
Editorial.
Microprocess. Microsystems
Chris R. Jesshope
1989 J jnl
Editorial.
Microprocess. Microsystems
Chris R. Jesshope
1989 A* conf
High Performance Communications in Processor Networks.
ISCA
Chris R. Jesshope, P. R. Miller, Jay T. Yantchev
1989 J jnl
Parallel processing, the transputer and the future.
Microprocess. Microsystems
Chris R. Jesshope
1989 J jnl
Parallel program design: a foundation: Chandry, K M and Misra, J Addison-Wesley, Wokingham, UK (1988) £19.95 pp 516.
Microprocess. Microsystems
Chris R. Jesshope
1988 J jnl
MUNAP: an unusual computer with clear implications: Baba, TMicroprogrammable parallel computers MIT Press, Cambridge, MA, USA (1987) £26.95 pp 290.
Microprocess. Microsystems
Chris R. Jesshope
1988 — conf
Programming with active data.
Parcella
Chris R. Jesshope, Philip Miller, Jelio Yantchev
1988 — conf
Reconfigurable transputer systems.
C³P
Chris R. Jesshope
1988 J jnl
Transputers and switches as objects in OCCAM.
Parallel Comput.
Chris R. Jesshope
1985 J jnl
An Intelligent Pascal Editor for a Graphical Oriented Workstation.
Softw. Pract. Exp.
Chris R. Jesshope, M. J. Crawley, G. L. Lovegrove
1980 J jnl
Some Results Concerning Data Routing in Array Processors.
IEEE Trans. Computers
Chris R. Jesshope
1980 J jnl
The Implementation of Fast Radix 2 Transforms on Array Processors.
IEEE Trans. Computers
Chris R. Jesshope