Chris H. Kim - RankMe

177 papers A* 6A 22C 11Misc 2Journal 69Unranked 67

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Decomposing Large-Scale Ising Problems on FPGAs: A Hybrid Hardware Approach. CoRR Ruihong Yin, Yue Zheng, Chaohui Li, Ahmet Efe, Abhimanyu Kumar, Ziqing Zeng, Ulya R. Karpuzcu, Sachin S. Sapatnekar, Chris H. Kim
2026	J	`jnl`	Extractive summarization on a CMOS Ising machine. CoRR Ziqing Zeng, Abhimanyu Kumar, Ahmet Efe, Ruihong Yin, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar
2025	—	`conf`	Aging Characterization at Cryogenic Temperature with Synthesizable Odometers in 12NM and 28NM. IRPS Tahmida Islam, Junkyu Kim, Hanzhao Yu, Zheng Xue, Jacob Xing, Chris H. Kim, Jiesi Xing, Christopher Elash, Peiman Pour Momen, Li Chen
2025	J	`jnl`	DROID: Discrete-Time Simulation for Ring-Oscillator-Based Ising Design. CoRR Abhimanyu Kumar, S. Ramprasath, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar
2025	J	`jnl`	On Solving Structured SAT on Ising Machines: A Semiprime Factorization Study. CoRR Ahmet Efe, Hüsrev Cilasun, Abhimanyu Kumar, Nafisa Sadaf Prova, Ziqing Zeng, Tahmida Islam, Ruihong Yin, Chaohui Li, Peter Kreye, Chris H. Kim, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2025	—	`conf`	Tracking Fmax Degradation of a RISC-V CPU with Synthesizable Odometer Aging Sensors. CICC Tahmida Islam, Junkyu Kim, Hanzhao Yu, Chris H. Kim
2024	—	`conf`	Electromigration Test Chip Experiments from Realistic Power Grid Structures: Failure Trend Comparison and Statistical Analysis. IRPS Yong Hyeon Yi, Chris H. Kim, Armen Kteyan, Alexander Volkov, Stéphane Moreau, Valeriy Sukharev
2024	J	`jnl`	Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design. IEEE Trans. Circuits Syst. II Express Briefs Xiaoxuan Yang, Zhangyang Wang, X. Sharon Hu, Chris H. Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, Hai Helen Li
2024	—	`conf`	Quantum-Inspired Machine Learning Framework using a Physics-based Ising Solver Chip. ICPS Ameya Khot, Taesic Kim, Alve Rahman Akash, Chris H. Kim, William Moy
2023	J	`jnl`	3SAT on an All-to-All-Connected CMOS Ising Solver Chip. CoRR M. Hüsrev Cilasun, Ziqing Zeng, Ramprasath S, Abhimanyu Kumar, Hao Lo, William Cho, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar
2023	—	`conf`	Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution. ISPD Armen Kteyan, Valeriy Sukharev, Alexander Volkov, Jun-Ho Choy, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Stéphane Moreau
2023	—	`conf`	Studying the Impact of Temperature Gradient on Electromigration Lifetime Using a Power Grid Test Structure with On-Chip Heaters. IRPS Yong Hyeon Yi, Chris H. Kim, Chen Zhou, Armen Kteyan, Valeriy Sukharev
2022	J	`jnl`	A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors. IEEE Trans. Circuits Syst. I Regul. Pap. Po-Wei Chiu, Chris H. Kim
2022	—	`conf`	A Calibration-Free Synthesizable Odometer Featuring Automatic Frequency Dead Zone Escape and Start-up Glitch Removal. IRPS Tahmida Islam, Junkyu Kim, Chris H. Kim, David Tipple, Michael Nelson, Robert Jin, Anis Jarrar
2022	J	`jnl`	An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process. IEEE J. Solid State Circuits Minsu Kim, Muqing Liu, Luke R. Everson, Chris H. Kim
2022	J	`jnl`	Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Valeriy Sukharev, Armen Kteyan, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Jun-Ho Choy, Sofya Torosyan, Yu Zhu
2022	J	`jnl`	GeNVoM: Read Mapping Near Non-Volatile Memory. IEEE ACM Trans. Comput. Biol. Bioinform. S. Karen Khatamifard, Zamshed I. Chowdhury, Nakul Pande, Meisam Razaviyayn, Chris H. Kim, Ulya R. Karpuzcu
2022	—	`conf`	Novel methodology for temperature-aware electromigration assessment in on-chip power grid: simulations and experimental validation (Invited). IRPS Armen Kteyan, Valeriy Sukharev, Y. Yi, Chris H. Kim
2021	J	`jnl`	A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. IEEE Trans. Very Large Scale Integr. Syst. Saurabh Kumar, Minki Cho, Luke R. Everson, Andres Malavasi, Dan Lake, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De, Chris H. Kim
2021	J	`jnl`	A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems. IEEE J. Solid State Circuits Ibrahim Ahmed, Po-Wei Chiu, William Moy, Chris H. Kim
2021	J	`jnl`	A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control. IEEE J. Solid State Circuits Luke R. Everson, Sachin S. Sapatnekar, Chris H. Kim
2021	—	`conf`	An All BTI (N-PBTI, N-NBTI, P-PBTI, P-NBTI) Odometer based on a Dual Power Rail Ring Oscillator Array. IRPS Gyusung Park, Hanzhao Yu, Minsu Kim, Chris H. Kim
2021	—	`conf`	Extreme Temperature Characterization of Amplifier Response up to 300 Degrees Celsius Using Integrated Heaters and On-chip Samplers. ESSCIRC Hanzhao Yu, Gyusung Park, Chris H. Kim
2021	J	`jnl`	Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. IEEE Trans. Very Large Scale Integr. Syst. Sriram R. Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James W. Tschanz, Vivek De, Chris H. Kim
2020	—	`conf`	22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor. ISSCC Po-Wei Chiu, Chris H. Kim
2020	—	`conf`	A Probabilistic Self-Annealing Compute Fabric Based on 560 Hexagonally Coupled Ring Oscillators for Solving Combinatorial Optimization Problems. VLSI Circuits Ibrahim Ahmed, Po-Wei Chiu, Chris H. Kim
2020	—	`conf`	Reliability Characterization of Logic-Compatible NAND Flash Memory based Synapses with 3-bit per Cell Weights and 1μA Current Steps. IRPS Minsu Kim, Jeehwan Song, Chris H. Kim
2019	—	`conf`	A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control. ISSCC Luke R. Everson, Sachin S. Sapatnekar, Chris H. Kim
2019	—	`conf`	A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing. CICC Gyusung Park, Minsu Kim, Nakul Pande, Po-Wei Chiu, Jeehwan Song, Chris H. Kim
2019	J	`jnl`	A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer. IEEE J. Solid State Circuits Somnath Kundu, Muqing Liu, Shi-Jie Wen, Richard Wong, Chris H. Kim
2019	J	`jnl`	An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm. IEEE J. Solid State Circuits Luke R. Everson, Muqing Liu, Nakul Pande, Chris H. Kim
2019	—	`conf`	BioTranslator: Inferring R-Peaks from Ambulatory Wrist-Worn PPG Signal. EMBC Luke R. Everson, Dwaipayan Biswas, Bram-Ernst Verhoef, Chris H. Kim, Chris Van Hoof, Mario Konijnenburg, Nick Van Helleputte
2019	J	`jnl`	CorNET: Deep Learning Framework for PPG-Based Heart Rate Estimation and Biometric Identification in Ambulant Environment. IEEE Trans. Biomed. Circuits Syst. Dwaipayan Biswas, Luke R. Everson, Muqing Liu, Madhuri Panwar, Bram-Ernst Verhoef, Shrishail Patki, Chris H. Kim, Amit Acharyya, Chris Van Hoof, Mario Konijnenburg, Nick Van Helleputte
2019	—	`conf`	Investigating the Aging Dynamics of Diode-Connected MOS Devices Using an Array-Based Characterization Vehicle in a 65nm Process. IRPS Nakul Pande, Gyusung Park, Chris H. Kim, Srikanth Krishnan, Vijay Reddy
2019	—	`conf`	Real-time HR Estimation from wrist PPG using Binary LSTMs. BioCAS Leandro Mateus Giacomini Rocha, Nick Van Helleputte, Muqing Liu, Dwaipayan Biswas, Bram-Ernst Verhoef, Sergio Bampi, Chris H. Kim, Chris Van Hoof, Mario Konijnenburg, Marian Verhelst
2018	—	`conf`	A 0.0094mm BioCAS Luke R. Everson, Somnath Kundu, Gang Chen, Zhi Yang, Timothy J. Ebner, Chris H. Kim
2018	—	`conf`	A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm. A-SSCC Luke R. Everson, Muqing Liu, Nakul Pande, Chris H. Kim
2018	—	`conf`	A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. A-SSCC Po-Wei Chiu, Muqing Liu, Qianying Tang, Chris H. Kim
2018	J	`jnl`	A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer. IEEE J. Solid State Circuits Po-Wei Chiu, Somnath Kundu, Qianying Tang, Chris H. Kim
2018	C	`conf`	A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC. ISCAS Qianying Tang, Won Ho Choi, Luke R. Everson, Keshab K. Parhi, Chris H. Kim
2018	—	`conf`	A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning. ISSCC Somnath Kundu, Muqing Liu, Richard Wong, Shi-Jie Wen, Chris H. Kim
2018	—	`conf`	All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits. IRPS Gyusung Park, Minsu Kim, Chris H. Kim, Bongjin Kim, Vijay Reddy
2018	C	`conf`	BiometricNet: Deep Learning based Biometric Identification using Wrist-Worn PPG. ISCAS Luke R. Everson, Dwaipayan Biswas, Madhuri Panwar, Dimitrios Rodopoulos, Amit Acharyya, Chris H. Kim, Chris Van Hoof, Mario Konijnenburg, Nick Van Helleputte
2018	—	`conf`	Effect of aging on linear and nonlinear MUX PUFs by statistical modeling. ASP-DAC Anoop Koyily, Satya Venkata Sandeep Avvaru, Chen Zhou, Chris H. Kim, Keshab K. Parhi
2018	J	`jnl`	Key-Based Dynamic Functional Obfuscation of Integrated Circuits Using Sequentially Triggered Mode-Based Design. IEEE Trans. Inf. Forensics Secur. Sandhya Koteshwara, Chris H. Kim, Keshab K. Parhi
2018	—	`conf`	Low-Energy Deep Belief Networks Using Intrinsic Sigmoidal Spintronic-based Probabilistic Neurons. ACM Great Lakes Symposium on VLSI Ramtin Zand, Kerem Yunus Çamsari, Steven D. Pyle, Ibrahim Ahmed, Chris H. Kim, Ronald F. DeMara
2018	C	`conf`	Predicting Soft-Response of MUX PUFs via Logistic Regression of Total Delay Difference. ISCAS Anoop Koyily, Chen Zhou, Chris H. Kim, Keshab K. Parhi
2017	J	`jnl`	A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection. IEEE J. Solid State Circuits Somnath Kundu, Bongjin Kim, Chris H. Kim
2017	—	`conf`	A DRAM based physical unclonable function capable of generating >10 CICC Qianying Tang, Chen Zhou, Woong Choi, Gyuseong Kang, Jongsun Park, Keshab K. Parhi, Chris H. Kim
2017	J	`jnl`	A Non-volatile Near-Memory Read Mapping Accelerator. CoRR S. Karen Khatamifard, Zamshed I. Chowdhury, Nakul Pande, Meisam Razaviyayn, Chris H. Kim, Ulya R. Karpuzcu
2017	A*	`conf`	A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. DAC Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami
2017	A	`conf`	A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function. ISLPED Muqing Liu, Chen Zhou, Qianying Tang, Keshab K. Parhi, Chris H. Kim
2017	C	`conf`	A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology. ISCAS Somnath Kundu, Chris H. Kim
2017	—	`conf`	A scalable time-based integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition capabilities. CICC Muqing Liu, Luke R. Everson, Chris H. Kim
2017	A	`conf`	Advanced spintronic memory and logic for non-volatile processors. DATE Robert Perricone, Ibrahim Ahmed, Zhaoxin Liang, Meghna G. Mankalale, Xiaobo Sharon Hu, Chris H. Kim, Michael T. Niemier, Sachin S. Sapatnekar, Jianping Wang
2017	C	`conf`	An entropy test for determining whether a MUX PUF is linear or nonlinear. ISCAS Anoop Koyily, Chen Zhou, Chris H. Kim, Keshab K. Parhi
2017	J	`jnl`	Characterizing the Impact of RTN on Logic and SRAM Operation Using a Dual Ring Oscillator Array Circuit. IEEE J. Solid State Circuits Qianying Tang, Chris H. Kim
2017	Misc	`conf`	Functional encryption of integrated circuits by key-based hybrid obfuscation. ACSSC Sandhya Koteshwara, Chris H. Kim, Keshab K. Parhi
2017	C	`conf`	Hierarchical functional obfuscation of integratec circuits using a mode-based approach. ISCAS Sandhya Koteshwara, Chris H. Kim, Keshab K. Parhi
2017	—	`conf`	Predicting hard and soft-responses and identifying stable challenges of MUX PUFs using ANNs. MWSCAS S. V. Sandeep Avvaru, Chen Zhou, Chris H. Kim, Keshab K. Parhi
2017	J	`jnl`	R-DBN: A Resistive Deep Belief Network Architecture Leveraging the Intrinsic Behavior of Probabilistic Devices. CoRR Ramtin Zand, Kerem Yunus Çamsari, Ibrahim Ahmed, Steven D. Pyle, Chris H. Kim, Supriyo Datta, Ronald F. DeMara
2017	J	`jnl`	Reliable PUF-Based Local Authentication With Self-Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yingjie Lao, Bo Yuan, Chris H. Kim, Keshab K. Parhi
2017	A*	`conf`	Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements. DAC Chen Zhou, Keshab K. Parhi, Chris H. Kim
2016	—	`conf`	19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection. ISSCC Somnath Kundu, Bongjin Kim, Chris H. Kim
2016	J	`jnl`	A 0.0054-mm IEEE Trans. Circuits Syst. II Express Briefs Somnath Kundu, Chris H. Kim
2016	J	`jnl`	Beat Frequency Detector-Based High-Speed True Random Number Generators: Statistical Modeling and Analysis. ACM J. Emerg. Technol. Comput. Syst. Yingjie Lao, Qianying Tang, Chris H. Kim, Keshab K. Parhi
2016	J	`jnl`	CoMET: Composite-Input Magnetoelectric-based Logic Technology. CoRR Meghna G. Mankalale, Zhaoxin Liang, Zhengyang Zhao, Chris H. Kim, Jianping Wang, Sachin S. Sapatnekar
2016	A	`conf`	Estimating delay differences of arbiter PUFs using silicon data. DATE S. V. Sandeep Avvaru, Chen Zhou, Saroj Satapathy, Yingjie Lao, Chris H. Kim, Keshab K. Parhi
2016	—	`conf`	Mode-based Obfuscation using Control-Flow Modifications. CS2@HiPEAC Sandhya Koteshwara, Chris H. Kim, Keshab K. Parhi
2016	A	`conf`	Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs. ISLPED Chen Zhou, Saroj Satapathy, Yingjie Lao, Keshab K. Parhi, Chris H. Kim
2016	J	`jnl`	System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators. IEEE Trans. Very Large Scale Integr. Syst. Ayan Paul, Sang Phill Park, Dinesh Somasekhar, Young Moon Kim, Nitin Borkar, Ulya R. Karpuzcu, Chris H. Kim
2015	—	`conf`	A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit. VLSIC Bongjin Kim, Somnath Kundu, Chris H. Kim
2015	—	`conf`	A 8-14 GHz varactorless current controlled LC oscillator in 16nm CMOS technology. MWSCAS Somnath Kundu, Vassili Kireev, Chris H. Kim
2015	J	`jnl`	A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology. IEEE Trans. Very Large Scale Integr. Syst. Tony Tae-Hyoung Kim, Pong-Fei Lu, Keith A. Jenkins, Chris H. Kim
2015	—	`conf`	A revolving reference odometer circuit for BTI-induced frequency fluctuation measurements under fast DVFS transients. IRPS Saroj Satapathy, Won Ho Choi, Xiaofei Wang, Chris H. Kim
2015	—	`conf`	A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies. CICC Jongyeon Kim, An Chen, Behtash Behin-Aein, Saurabh Kumar, Jianping Wang, Chris H. Kim
2015	—	`conf`	An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier. CICC Bongjin Kim, Hoon Ki Kim, Chris H. Kim
2015	—	`conf`	Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs. CICC Won Ho Choi, Hoon Ki Kim, Chris H. Kim
2015	C	`conf`	Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR). ISCAS Rahul Parhi, Chris H. Kim, Keshab K. Parhi
2015	J	`jnl`	Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor. Proc. IEEE Jongyeon Kim, Ayan Paul, Paul A. Crowell, Steven J. Koester, Sachin S. Sapatnekar, Jianping Wang, Chris H. Kim
2015	J	`jnl`	The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications. IEEE Trans. Very Large Scale Integr. Syst. Xiaofei Wang, Qianying Tang, Pulkit Jain, Dong Jiao, Chris H. Kim
2015	—	`conf`	Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals. CICC Somnath Kundu, Bongjin Kim, Chris H. Kim
2014	J	`jnl`	A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications. IEEE J. Solid State Circuits Seung-Hwan Song, Ki Chul Chun, Chris H. Kim
2014	J	`jnl`	A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter. IEEE J. Solid State Circuits Bongjin Kim, Weichao Xu, Chris H. Kim
2014	—	`conf`	A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals. CICC Bongjin Kim, Somnath Kundu, Seokkyun Ko, Chris H. Kim
2014	—	`conf`	A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage. CICC Won Ho Choi, Saroj Satapathy, John Keane, Chris H. Kim
2014	J	`jnl`	Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. Pingqiang Zhou, Ayan Paul, Chris H. Kim, Sachin S. Sapatnekar
2014	A	`conf`	Improving STT-MRAM density through multibit error correction. DATE Brandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar
2014	Misc	`conf`	Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations. VLSID Ayan Paul, Chaitanya Kshirsagar, Sachin S. Sapatnekar, Steven J. Koester, Chris H. Kim
2014	—	`conf`	SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data. CICC Xiaofei Wang, Weichao Xu, Chris H. Kim
2014	J	`jnl`	Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design. IEEE Micro Xiaofei Wang, John Keane, Tony Tae-Hyoung Kim, Pulkit Jain, Qianying Tang, Chris H. Kim
2014	—	`conf`	True Random Number Generator circuits based on single- and multi-phase beat frequency detection. CICC Qianying Tang, Bongjin Kim, Yingjie Lao, Keshab K. Parhi, Chris H. Kim
2013	J	`jnl`	A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme. IEEE J. Solid State Circuits Seung-Hwan Song, Ki Chul Chun, Chris H. Kim
2013	J	`jnl`	A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory. IEEE J. Solid State Circuits Ki Chul Chun, Hui Zhao, Jonathan D. Harms, Tony Tae-Hyoung Kim, Jianping Wang, Chris H. Kim
2013	J	`jnl`	A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode. IEEE Trans. Circuits Syst. I Regul. Pap. Wei Zhang, Ki Chul Chun, Chris H. Kim
2013	—	`conf`	A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications. CICC Seung-Hwan Song, Ki Chul Chun, Chris H. Kim
2013	—	`conf`	A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal. CICC Bongjin Kim, Weichao Xu, Chris H. Kim
2012	J	`jnl`	A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor. IEEE J. Solid State Circuits Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim
2012	J	`jnl`	A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches. IEEE J. Solid State Circuits Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, Chris H. Kim
2012	—	`conf`	A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme. VLSIC Seung-Hwan Song, Ki Chul Chun, Chris H. Kim
2012	—	`conf`	A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode. CICC Wei Zhang, Ki Chul Chun, Chris H. Kim
2012	J	`jnl`	An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of V IEEE Trans. Circuits Syst. I Regul. Pap. Tony Tae-Hyoung Kim, Wei Zhang, Chris H. Kim
2012	—	`conf`	An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs. ESSDERC Pulkit Jain, John Keane, Chris H. Kim
2012	C	`conf`	Design of ring oscillator structures for measuring isolated NBTI and PBTI. ISCAS Tony T. Kim, Pong-Fei Lu, Chris H. Kim
2012	J	`jnl`	Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation. IEEE J. Solid State Circuits Dong Jiao, Bongjin Kim, Chris H. Kim
2012	A	`conf`	Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. ICCAD Pingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar
2012	J	`jnl`	Process and Reliability Sensors for Nanoscale CMOS. IEEE Des. Test Comput. John Keane, Chris H. Kim, Qunzeng Liu, Sachin S. Sapatnekar
2012	—	`conf`	Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors. CICC Ayan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S. Sapatnekar, Chris H. Kim
2011	—	`conf`	A 1V printed organic DRAM cell based on ion-gel gated transistors with a sub-10nW-per-cell Refresh Power. ISSCC Wei Zhang, Mingjing Ha, Daniele Braga, Michael J. Renn, C. Daniel Frisbie, Chris H. Kim
2011	J	`jnl`	A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches. IEEE J. Solid State Circuits Ki Chul Chun, Pulkit Jain, Jung-Hwa Lee, Chris H. Kim
2011	—	`conf`	A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies. ISSCC Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim
2011	—	`conf`	A programmable adaptive phase-shifting PLL for clock data compensation under resonant supply noise. ISSCC Dong Jiao, Chris H. Kim
2011	J	`jnl`	Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2011	J	`jnl`	An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization. IEEE J. Solid State Circuits John Keane, Wei Zhang, Chris H. Kim
2011	J	`jnl`	An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization. IEEE Trans. Very Large Scale Integr. Syst. John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim
2011	—	`conf`	Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network. CICC Pingqiang Zhou, Dong Jiao, Chris H. Kim, Sachin S. Sapatnekar
2011	J	`jnl`	Guest editors' introduction: Nanoscale Memories Pose Unique Challenges. IEEE Des. Test Comput. Chris H. Kim, Leland Chang
2010	J	`jnl`	An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB. IEEE J. Solid State Circuits John Keane, Xiaofei Wang, Devin Persaud, Chris H. Kim
2010	J	`jnl`	An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation. IEEE Trans. Very Large Scale Integr. Syst. John Keane, Tony Tae-Hyoung Kim, Chris H. Kim
2010	J	`jnl`	Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise. IEEE J. Solid State Circuits Dong Jiao, Jie Gu, Chris H. Kim
2010	C	`conf`	Logic-compatible embedded DRAM design for memory intensive low power systems. ISCAS Ki Chul Chun, Pulkit Jain, Chris H. Kim
2010	J	`jnl`	On-chip reliability monitors for measuring circuit degradation. Microelectron. Reliab. John Keane, Tony Tae-Hyoung Kim, Xiaofei Wang, Chris H. Kim
2010	A	`ed.`	Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010 ISLPED Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim
2010	A	`conf`	Variation aware performance analysis of gain cell embedded DRAMs. ISLPED Wei Zhang, Ki Chul Chun, Chris H. Kim
2009	A	`conf`	A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. ISLPED Ki Chul Chun, Pulkit Jain, Chris H. Kim
2009	J	`jnl`	A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V IEEE J. Solid State Circuits Tony Tae-Hyoung Kim, Jason Liu, Chris H. Kim
2009	—	`conf`	Adaptive techniques for overcoming performance degradation due to aging in digital circuits. ASP-DAC Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2009	—	`conf`	An SRAM reliability test macro for fully-automated statistical measurements of Vmin degradation. CICC Tony Tae-Hyoung Kim, Wei Zhang, Chris H. Kim
2009	—	`conf`	Circuit techniques for enhancing the clock data compensation effect under resonant supply noise. CICC Dong Jiao, Jie Gu, Chris H. Kim
2009	J	`jnl`	Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs. IEEE Trans. Very Large Scale Integr. Syst. Jie Gu, Ramesh Harjani, Chris H. Kim
2009	J	`jnl`	Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity. IEEE Trans. Very Large Scale Integr. Syst. Jie Gu, John Keane, Chris H. Kim
2009	J	`jnl`	On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit. IEEE J. Solid State Circuits Jie Gu, Hanyong Eom, Chris H. Kim
2009	J	`jnl`	Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance. IEEE Trans. Very Large Scale Integr. Syst. Jie Gu, Hanyong Eom, John Keane, Chris H. Kim
2008	J	`jnl`	A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing. IEEE J. Solid State Circuits Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim
2008	J	`jnl`	A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting. IEEE Trans. Very Large Scale Integr. Syst. Jonggab Kil, Jie Gu, Chris H. Kim
2008	A	`conf`	A multi-story power delivery technique for 3D integrated circuits. ISLPED Pulkit Jain, Tony Tae-Hyoung Kim, John Keane, Chris H. Kim
2008	—	`conf`	A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode. CICC Tony Tae-Hyoung Kim, Jason Liu, Chris H. Kim
2008	—	`conf`	An array-based test circuit for fully automated gate dielectric breakdown characterization. CICC John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim
2008	J	`jnl`	Body Bias Voltage Computations for Process and Temperature Compensation. IEEE Trans. Very Large Scale Integr. Syst. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2008	C	`conf`	Circuit techniques for ultra-low power subthreshold SRAMs. ISCAS Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim
2008	A	`conf`	Enhancing ISLPED Dong Jiao, Jie Gu, Pulkit Jain, Chris H. Kim
2008	J	`jnl`	Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits. IEEE J. Solid State Circuits Tony Tae-Hyoung Kim, Randy Persaud, Chris H. Kim
2008	J	`jnl`	Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
2008	J	`jnl`	Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. IEEE Trans. Very Large Scale Integr. Syst. Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim
2008	—	`conf`	Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies. ISQED Chris H. Kim
2007	—	`conf`	A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme. ISSCC Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim
2007	—	`conf`	An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement. CICC Tony Tae-Hyoung Kim, Jason Liu, Chris H. Kim
2007	A	`conf`	An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. ISLPED John Keane, Tony Tae-Hyoung Kim, Chris H. Kim
2007	J	`jnl`	Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors. IEEE Trans. Circuits Syst. I Regul. Pap. Hiroaki Suzuki, Chris H. Kim, Kaushik Roy
2007	—	`conf`	Modeling Subthreshold Leakage Current in General Transistor Networks. ISVLSI Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
2007	—	`conf`	Modeling and estimating leakage current in series-parallel CMOS networks. ACM Great Lakes Symposium on VLSI Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
2007	A*	`conf`	NBTI-Aware Synthesis of Digital Circuits. DAC Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2007	A	`conf`	Sleep transistor sizing and control for resonant supply noise damping. ISLPED Jie Gu, Hanyong Eom, Chris H. Kim
2007	—	`conf`	Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. PATMOS Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
2007	J	`jnl`	Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. IEEE Trans. Very Large Scale Integr. Syst. Tony Tae-Hyoung Kim, John Keane, Hanyong Eom, Chris H. Kim
2007	A*	`conf`	Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. DAC Jie Gu, Sachin S. Sapatnekar, Chris H. Kim
2006	A	`conf`	A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting. ISLPED Jonggab Kil, Jie Gu, Chris H. Kim
2006	J	`jnl`	A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
2006	A	`conf`	An analytical model for negative bias temperature instability. ICCAD Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2006	—	`conf`	Impact of NBTI on SRAM Read Stability and Design for Reliability. ISQED Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2006	J	`jnl`	Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim
2006	—	`conf`	Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. ASP-DAC Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2006	A	`conf`	Modeling and analysis of leakage induced damping effect in low voltage LSIs. ISLPED Jie Gu, John Keane, Chris H. Kim
2006	A*	`conf`	Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. DAC John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
2006	A	`conf`	Utilizing reverse short channel effect for optimal subthreshold circuit design. ISLPED Tony Tae-Hyoung Kim, Hanyong Eom, John Keane, Chris H. Kim
2006	—	`conf`	Width Quantization Aware FinFET Circuit Design. CICC Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim
2005	J	`jnl`	A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. Very Large Scale Integr. Syst. Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy
2005	—	`conf`	Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling. CICC Ik Joon Chang, Kunhyuk Kang, Saibal Mukhopadhyay, Chris H. Kim, Kaushik Roy
2005	A	`conf`	Multi-story power delivery for supply noise reduction and low voltage operation. ISLPED Jie Gu, Chris H. Kim
2005	C	`conf`	Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy
2005	—	`conf`	TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. ISQED Keejong Kim, Chris H. Kim, Kaushik Roy
2004	A	`conf`	Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. ISLPED Hari Ananthan, Chris H. Kim, Kaushik Roy
2004	A*	`conf`	Leakage in nano-scale technologies: mechanisms, impact and design considerations. DAC Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy
2003	A	`conf`	A forward body-biased low-leakage SRAM cache: device and architecture considerations. ISLPED Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy
2003	J	`jnl`	Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. Very Large Scale Integr. Syst. Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy
2002	A	`conf`	Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. DATE Chris H. Kim, Kaushik Roy
2002	A	`conf`	Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. ISLPED Chris H. Kim, Kaushik Roy