Chris C. N. Chu

74 papers A* 8A 15C 2Journal 24Unranked 23
YearRankTypeTitle / Venue / Authors
2016 A* conf
Area optimization of resilient designs guided by a mixed integer geometric program.
DAC
Hsin-Ho Huang, Huimei Cheng, Chris C. N. Chu, Peter A. Beerel
2016 A* conf
Flip-flop clustering by weighted K-means algorithm.
DAC
Gang Wu, Yue Xu, Dean Wu, Manoj Ragupathy, Yu-Yen Mo, Chris C. N. Chu
2016 A* conf
Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration.
DAC
Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak
2016 A conf
Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits.
DATE
Gang Wu, Chris C. N. Chu
2015 A* conf
An efficient shift invariant rasterization algorithm for all-angle mask patterns in ILT.
DAC
Yixiao Ding, Chris C. N. Chu, Xin Zhou
2015 A* conf
Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography.
DAC
Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak
2015 A conf
Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading.
ICCAD
Ankur Sharma, David G. Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu
2015 J jnl
Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chris C. N. Chu, Wai-Kei Mak
2015 — conf
Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation.
ASYNC
Gang Wu, Ankur Sharma, Chris C. N. Chu
2015 A conf
POLAR 3.0: An Ultrafast Global Placement Engine.
ICCAD
Tao Lin, Chris C. N. Chu, Gang Wu
2015 J jnl
POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tao Lin, Chris C. N. Chu, Joseph R. Shinnerl, Ismail Bustany, Ivailo Nedelchev
2015 — conf
TPL-Aware Displacement-driven Detailed Placement Refinement with Coloring Constraints.
ISPD
Tao Lin, Chris C. N. Chu
2011 J jnl
SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak
2009 J jnl
Handling routability in floorplan design with twin binary trees.
Integr.
Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu
2008 — ch.
Clock Network Design.
Handbook of Algorithms for Physical Design Automation
Chris C. N. Chu, Min Pan
2008 J jnl
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chris C. N. Chu, Yiu-Chung Wong
2008 — ch.
Practical Issues in Clock Network Design.
Handbook of Algorithms for Physical Design Automation
Chris C. N. Chu, Min Pan
2007 — conf
A Novel Performance-Driven Topology Design Algorithm.
ASP-DAC
Min Pan, Chris C. N. Chu, Priyadarshan Patra
2007 — conf
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control.
ASP-DAC
Natarajan Viswanathan, Min Pan, Chris C. N. Chu
2007 — conf
FastRoute 2.0: A High-quality and Efficient Global Router.
ASP-DAC
Min Pan, Chris C. N. Chu
2007 A* conf
IPR: An Integrated Placement and Routing Algorithm.
DAC
Min Pan, Chris C. N. Chu
2007 A* conf
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
DAC
Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu
2007 A conf
The coming of age of physical synthesis.
ICCAD
Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia
2007 J jnl
Wire Retiming Problem With Net Topology Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu
2006 A conf
A revisit to floorplan optimization by Lagrangian relaxation.
ICCAD
Chuan Lin, Hai Zhou, Chris C. N. Chu
2006 A conf
Analog placement with symmetry and other placement constraints.
ICCAD
Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu
2006 — conf
FastPlace 2.0: an efficient analytical placer for mixed-mode designs.
ASP-DAC
Natarajan Viswanathan, Min Pan, Chris C. N. Chu
2006 A conf
FastRoute: a step to integrate global routing into placement.
ICCAD
Min Pan, Chris C. N. Chu
2006 A* conf
Optimal cell flipping in placement and floorplanning.
DAC
Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu
2006 A conf
Post-placement voltage island generation.
ICCAD
Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu
2005 A conf
An efficient and effective detailed placement algorithm.
ICCAD
Min Pan, Natarajan Viswanathan, Chris C. N. Chu
2005 J jnl
An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sampath Dechu, Zion Cien Shen, Chris C. N. Chu
2005 C conf
Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages.
ICCD
Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li
2005 — conf
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design.
ISPD
Chris C. N. Chu, Yiu-Chung Wong
2005 — conf
FastPlace: an analytical placer for mixed-mode designs.
ISPD
Natarajan Viswanathan, Min Pan, Chris C. N. Chu
2005 J jnl
FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Natarajan Viswanathan, Chris C. N. Chu
2005 — conf
Timing yield estimation using statistical static timing analysis.
ISCAS (3)
Min Pan, Chris C. N. Chu, Hai Zhou
2005 — conf
Transition time bounded low-power clock tree construction.
ISCAS (3)
Min Pan, Chris C. N. Chu, J. Morris Chang
2004 — conf
Accurate and efficient flow based congestion estimation in floorplanning.
ASP-DAC
Zion Cien Shen, Chris C. N. Chu
2004 — conf
An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations.
ASP-DAC
Sampath Dechu, Zion Cien Shen, Chris C. N. Chu
2004 — conf
FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model.
ISPD
Natarajan Viswanathan, Chris C. N. Chu
2004 J jnl
Nonrectangular shaping and sizing of soft modules for floorplan-design improvement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chris C. N. Chu, Evangeline F. Y. Young
2004 — conf
Optimal gate sizing for coupling-noise reduction.
ISPD
Debjit Sinha, Hai Zhou, Chris C. N. Chu
2004 J jnl
Placement constraints in floorplan design.
IEEE Trans. Very Large Scale Integr. Syst.
Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
2004 J jnl
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
2003 A conf
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees.
DATE
Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu
2003 J jnl
Bounds on the number of slicing, mosaic, and general floorplans.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zion Cien Shen, Chris C. N. Chu
2003 J jnl
Dependable Handling of Uncertainty.
Reliab. Comput.
Daniel Berleant, Mei-Peng Cheong, Chris C. N. Chu, Yong Guan, Ahmed E. Kamal, Gerald Shedblé, Scott Ferson, James F. Peters
2003 — conf
Optimizing SOC Test Resources Using Dual Sequences.
VLSI-SoC (Selected Papers)
Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz
2003 A conf
Retiming with Interconnect and Gate Delay.
ICCAD
Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu
2003 J jnl
Twin binary sequences: a nonredundant representation for general nonslicing floorplan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen
2002 — conf
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design.
ASP-DAC/VLSI Design
Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
2002 C conf
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model.
ICCD
Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu
2002 A conf
Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design.
DATE
Chris C. N. Chu, Evangeline F. Y. Young
2002 — conf
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
ISPD
Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
2002 — conf
Twin binary sequences: a non-redundant representation for general non-slicing floorplan.
ISPD
Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen
2001 J jnl
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing.
ACM Trans. Design Autom. Electr. Syst.
Chris C. N. Chu, D. F. Wong
2001 J jnl
Handling soft modules in general nonslicing floorplan usingLagrangian relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong
2001 J jnl
Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu-Yen Mo, Chris C. N. Chu
2001 J jnl
VLSI Circuit Performance Optimization by Geometric Programming.
Ann. Oper. Res.
Chris C. N. Chu, D. F. Wong
2000 — conf
A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization.
ISPD
Yu-Yen Mo, Chris C. N. Chu
2000 — conf
Floorplan area minimization using Lagrangian relaxation.
ISPD
Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong
1999 J jnl
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chris C. N. Chu, Martin D. F. Wong
1999 J jnl
An efficient and optimal algorithm for simultaneous buffer and wire sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chris C. N. Chu, Martin D. F. Wong
1999 J jnl
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong
1999 J jnl
Generation of Universal Series-Parallel Boolean Functions.
J. ACM
Fung Yu Young, Chris C. N. Chu, D. F. Wong
1999 J jnl
Greedy wire-sizing is linear time.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chris C. N. Chu, Martin D. F. Wong
1998 A conf
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing.
DATE
Chris C. N. Chu, D. F. Wong
1998 J jnl
A matrix synthesis approach to thermal placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chris C. N. Chu, Martin D. F. Wong
1998 A conf
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation.
ICCAD
Chung-Ping Chen, Chris C. N. Chu, D. F. Wong
1998 — conf
Greedy wire-sizing is linear time.
ISPD
Chris C. N. Chu, D. F. Wong
1997 — conf
A matrix synthesis approach to thermal placement.
ISPD
Chris C. N. Chu, D. F. Wong
1997 A conf
A new approach to simultaneous buffer insertion and wire sizing.
ICCAD
Chris C. N. Chu, D. F. Wong
1997 — conf
Closed form solution to simultaneous buffer insertion/sizing and wire sizing.
ISPD
Chris C. N. Chu, D. F. Wong