Chris Bailey

18 papers A* 1C 6Journal 2Unranked 9
YearRankTypeTitle / Venue / Authors
2018 J jnl
Performance Analysis of a 3D Wireless Massively Parallel Computer.
J. Sens. Actuator Networks
Amir Mansoor Kamali Sarvestani, Chris Bailey, Jim Austin
2009 — conf
A JAVA bread-board simulator digital circuit simulation with an extensible e-learning tool.
IADIS AC (1)
Chris Bailey, Michael J. Freeman
2009 — conf
Re-evaluation of the role of the processor within embedded multiprocessor systems.
IADIS AC (1)
Michael Freeman, Chris Bailey
2008 J jnl
Real-time human action recognition on an embedded, reconfigurable video processing architecture.
J. Real Time Image Process.
Hongying Meng, Michael Freeman, Nick E. Pears, Chris Bailey
2007 A* conf
A Human Action Recognition System for Embedded Computer Vision Application.
CVPR
Hongying Meng, Nick E. Pears, Chris Bailey
2007 — conf
Motion Feature Combination for Human Action Recognition in Video.
VISIGRAPP (Selected Papers)
Hongying Meng, Nick E. Pears, Chris Bailey
2007 — conf
Motion information combination for fast human action recognition.
VISAPP (2)
Hongying Meng, Nick E. Pears, Chris Bailey
2007 — conf
Practical single view metrology for cuboids.
VISAPP (2)
Nick E. Pears, Paul Wright, Chris Bailey
2006 — conf
Human Action Classification Using SVM_2K Classifier on Motion Features.
MRCS
Hongying Meng, Nick E. Pears, Chris Bailey
2005 — conf
Combined simulator statistics and block code sampling to study performance enhancement of microarchitecture.
SoCC
Huibin Shi, Chris Bailey, Glenn Farrall, Neil Hastie, Sam Jenkins
2005 C conf
Developing ubiquitous computing applications.
IADIS AC
Michael Freeman, Chris Bailey
2005 C conf
Instruction level parallelism of stack-code under varied issue widths, and one-level branch prediction.
IADIS AC
Chris Bailey, Huibin Shi
2004 C conf
A Mechanism for Implementing Precise Exceptions in Pipelined Processors.
DSD
Soyeb Alli, Chris Bailey
2004 C conf
A Proposed Mechanism for Super-Pipelined Instruction-Issue for ILP Stack Machines.
DSD
Chris Bailey
2004 C conf
Compiler-Directed Dynamic Memory Disambiguation for Loop Structures.
DSD
Soyeb Alli, Chris Bailey
2004 C conf
Investigating Available Instruction Level Parallelism for Stack Based Machine Architectures.
DSD
Huibin Shi, Chris Bailey
2000 — conf
Achieving Minimal and Deterministic Interrupt Execution in Stack-Based Processor Architectures.
EUROMICRO
Chris Bailey
2000 — conf
Continuous Discrete-Event Simulation of a Continuous-Media Server I/O Subsystem.
EUROMICRO
Michael Weeks, Chris Bailey, Reza Sotudeh