Chongxiao Li - RankMe

14 papers A* 3Journal 11

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	AGON: Automated Design Framework for Customizing Processors From ISA Documents. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chongxiao Li, Di Huang, Pengwei Jin, TianYun Ma, Husheng Han, Shuyao Cheng, Yifan Hao, Yongwei Zhao, Guanglin Xu, Zidong Du, Rui Zhang, Xiaqing Li, Yuanbo Wen, Xing Hu, Qi Guo
2026	J	`jnl`	CodeV: Empowering LLMs With HDL Generation Through Multilevel Summarization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yang Zhao, Di Huang, Chongxiao Li, Pengwei Jin, Muxin Song, Yinan Xu, Ziyuan Nan, Mingju Gao, TianYun Ma, Lei Qi, Yansong Pan, Zhenxing Zhang, Rui Zhang, Xishan Zhang, Zidong Du, Qi Guo, Xing Hu
2026	J	`jnl`	LocalV: Exploiting Information Locality for IP-level Verilog Generation. CoRR Han-Qi Lyu, Di Huang, Yaoyu Zhu, Kangcheng Liu, Bohan Dou, Chongxiao Li, Pengwei Jin, Shuyao Cheng, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen
2026	A*	`conf`	QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression. AAAI Lei Huang, Rui Zhang, Jiaming Guo, Yang Zhang, Di Huang, Shuyao Cheng, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Yunji Chen, Qi Guo
2025	A*	`conf`	Automated Superscalar Processor Design by Learning Data Dependencies. IJCAI Shuyao Cheng, Rui Zhang, Wenkai He, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Yifan Hao, Guanglin Xu, Yuanbo Wen, Ling Li, Qi Guo, Yunji Chen
2025	J	`jnl`	CodeV-R1: Reasoning-Enhanced Verilog Generation. CoRR Yaoyu Zhu, Di Huang, Han-Qi Lyu, Xiaoyun Zhang, Chongxiao Li, Wenxuan Shi, Yutong Wu, Jianan Mu, Jinghua Wang, Yang Zhao, Pengwei Jin, Shuyao Cheng, Shengwen Liang, Xishan Zhang, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen
2025	J	`jnl`	QiMeng-CPU-v2: Automated Superscalar Processor Design by Learning Data Dependencies. CoRR Shuyao Cheng, Rui Zhang, Wenkai He, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Yifan Hao, Guanglin Xu, Yuanbo Wen, Ling Li, Qi Guo, Yunji Chen
2025	J	`jnl`	QiMeng-CRUX: Narrowing the Gap between Natural Language and Verilog via Core Refined Understanding eXpression. CoRR Lei Huang, Rui Zhang, Jiaming Guo, Yang Zhang, Di Huang, Shuyao Cheng, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Qi Guo, Yunji Chen
2025	J	`jnl`	QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation. CoRR Yang Zhang, Rui Zhang, Jiaming Guo, Lei Huang, Di Huang, Yunpu Zhao, Shuyao Cheng, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Qi Guo, Yunji Chen
2025	J	`jnl`	RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs. CoRR Pengwei Jin, Di Huang, Chongxiao Li, Shuyao Cheng, Yang Zhao, Xinyao Zheng, Jiaguo Zhu, Shuyi Xing, Bohan Dou, Rui Zhang, Zidong Du, Qi Guo, Xing Hu
2025	J	`jnl`	SaaP: Rearchitect SoC-as-a-Processor to Orchestrate Hardware Heterogeneity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pengwei Jin, Zhe Fan, Yongwei Zhao, Zidong Du, Hongrui Guo, Ziyuan Nan, Yifan Hao, Chongxiao Li, TianYun Ma, Zhenxing Zhang, Xiaqing Li, Wei Li, Xing Hu, Qi Guo, Zhiwei Xu, Tianshi Chen
2024	J	`jnl`	AGON: Automated Design Framework for Customizing Processors from ISA Documents. CoRR Chongxiao Li, Di Huang, Pengwei Jin, TianYun Ma, Husheng Han, Shuyao Cheng, Yifan Hao, Yongwei Zhao, Guanglin Xu, Zidong Du, Rui Zhang, Xiaqing Li, Yuanbo Wen, Yanjun Wu, Chen Zhao, Xing Hu, Qi Guo
2024	J	`jnl`	CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization. CoRR Yang Zhao, Di Huang, Chongxiao Li, Pengwei Jin, Ziyuan Nan, TianYun Ma, Lei Qi, Yansong Pan, Zhenxing Zhang, Rui Zhang, Xishan Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen
2024	A*	`conf`	Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation. DAC Shuyao Cheng, Chongxiao Li, Zidong Du, Rui Zhang, Xing Hu, Xiaqing Li, Guanglin Xu, Yuanbo Wen, Qi Guo