Chixiao Chen - RankMe

99 papers A* 11A 3B 1C 10Journal 29Unranked 45

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	14.1 THz-TSI: A 0.33pJ/b 264Gb/s Through-Silicon Interconnect Module for 3D Integration Utilizing Terahertz Coupling. ISSCC Chen Jiang, Xiaodi Feng, Xiaohan Shen, Chixiao Chen, Qi Liu, Ming Liu, Ningsheng Xu
2026	—	`conf`	A 16Gb/s/pin 0.51pJ/b Single-Ended NRZ Transceiver with Distributed Dual-Loop VDDQ-Ripple Compensation and Dynamic Clock Duty-Cycle Calibration for Memory Interfaces. ISSCC Yuchen He, Yunbin Luo, Yunzhengmao Wang, Tengyue Yi, Chen Jiang, Chixiao Chen, Qi Liu, Ming Liu, Wenning Jiang
2026	J	`jnl`	A 22-nm 109.3-to-249.5-TFLOPS/W Outlier-Aware Floating-Point SRAM Compute-in-Memory Macro for Large Language Models. IEEE J. Solid State Circuits Siqi He, Haozhe Zhu, Hongyi Zhang, Yujie Ma, Zexing Chen, Mengjie Li, Danfeng Zhai, Chixiao Chen, Qi Liu, Xiaoyang Zeng, Ming Liu
2026	—	`conf`	BLADE: Boosting LLM Decoding's Communication Efficiency in DRAM-based PIM. ASP-DAC Yilong Zhao, Fangxin Liu, Zongwu Wang, Mingjian Li, Mingxing Zhang, Chixiao Chen, Li Jiang
2026	J	`jnl`	COPIC: A Codesigned Accelerator for Efficient Octree-Based Learned Point Cloud Compression at Edge. IEEE Trans. Very Large Scale Integr. Syst. Jiapei Zheng, Yutong Su, Siqi He, Jie Yang, Haozhe Zhu, Qi Liu, Chixiao Chen
2026	J	`jnl`	SHINSAI: A 586 mm IEEE J. Solid State Circuits Haozhe Zhu, Bo Jiao, Yuman Zeng, Yongjiang Li, Jie Liao, Siyao Jia, Zexing Chen, Liyu Lin, Xuanda Lin, Suchang Huang, Mochen Tian, Jundong Zhu, Dexin Wen, Yan Wang, Yu Wang, Jian Xu, Feng Wang, Jun Tao, Chixiao Chen, Qi Liu, Ming Liu
2025	—	`conf`	37.4 SHINSAI: A 586mm ISSCC Bo Jiao, Haozhe Zhu, Yuman Zeng, Yongjiang Li, Jie Liao, Siyao Jia, Mochen Tian, Zexing Chen, Jundong Zhu, Dexin Wen, Yan Wang, Yu Wang, Jian Xu, Feng Wang, Jun Tao, Chixiao Chen, Qi Liu, Ming Liu
2025	C	`conf`	A 0.22 pJ/bit Processing-in-Controller GEMV Macro with Weight Prefetch for Efficient Near-Memory Computing. ISCAS Jie Yang, Jiapei Zheng, Siqi He, Lizhou Wu, Chen Mu, Haozhe Zhu, Liyu Lin, Qi Liu, Chixiao Chen
2025	J	`jnl`	A 28-nm RRAM/SRAM Collaborative CIM Accelerator Supporting RRAM-Endurance-Latency Awareness for Edge Fine-Tuning. IEEE J. Solid State Circuits Chen Mu, Zhirui Huang, Hao Jiang, Jie Liao, Yuliang Zhou, Liang Chen, Yechu Zhang, Haozhe Zhu, Jianguo Yang, Qi Liu, Chixiao Chen
2025	A*	`conf`	DRAFT: Decoupling Backpropagation from Pre-trained Backbone for Efficient Transformer Fine-Tuning on Edge. DAC Zhirui Huang, Shiwei Liu, Haozhe Zhu, Qi Liu, Chixiao Chen
2025	A*	`conf`	EIGEN: Enabling Efficient 3DIC Interconnect with Heterogeneous Dual-Layer Network-on-Active-Interposer. HPCA Siyao Jia, Bo Jiao, Haozhe Zhu, Chixiao Chen, Qi Liu, Ming Liu
2025	A	`conf`	GauPRE: A Pattern-based Rendering Engine for Gaussian Splatting on Edge Device. ICCAD Yuzheng Lin, Lizhou Wu, Chixiao Chen, Xiaoyang Zeng, Haozhe Zhu
2025	A*	`conf`	Hydra: Harnessing Expert Popularity for Efficient Mixture-of-Expert Inference on Chiplet System. DAC Siqi He, Haozhe Zhu, Jiapei Zheng, Lizhou Wu, Bo Jiao, Qi Liu, Xiaoyang Zeng, Chixiao Chen
2025	A*	`conf`	McPAL: Scaling Unstructured Sparse Inference with Multi-Chiplet HBM-PIM Architecture for LLMs. DAC Shiwei Liu, Zhirui Huang, Jiangnan Yu, Qi Liu, Chixiao Chen
2025	A*	`conf`	PIMoE: Towards Efficient MoE Transformer Deployment on NPU-PIM System through Throttle-Aware Task Offloading. DAC Lizhou Wu, Haozhe Zhu, Siqi He, Xuanda Lin, Xiaoyang Zeng, Chixiao Chen
2025	J	`jnl`	RT-FLOW: FPGA Implementation of Real-Time Optical-Flow-Based SLAM for High-Speed Tracking and High-Quality Mapping. IEEE Trans. Circuits Syst. I Regul. Pap. Mengjie Li, Yiming Zhang, Siqi He, Qi Liu, Xiaoyang Zeng, Chixiao Chen, Haozhe Zhu
2025	J	`jnl`	TENET: An Efficient Sparsity-Aware LUT-Centric Architecture for Ternary LLM Inference On Edge. CoRR Zhirui Huang, Rui Ma, Shijie Cao, Ran Shu, Ian Wang, Ting Cao, Chixiao Chen, Yongqiang Xiong
2024	—	`conf`	A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset Calibration. CICC Wenning Jiang, Yunbin Luo, Peizhe Li, Ji Guo, Chixiao Chen, Qi Liu
2024	C	`conf`	A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder. ISCAS Mengjie Li, Hongyi Zhang, Siqi He, Haozhe Zhu, Hao Zhang, Jinglei Liu, Jiayuan Chen, Zhenping Hu, Xiaoyang Zeng, Chixiao Chen
2024	—	`conf`	A 28-nm 10.4-fJ/b Cryogenic embedded DRAM with 3T1C Gain Cell and MBIST at 4-Kelvin. ISOCC Jiapei Zheng, Xinkai Nie, Zhenghang Zhi, Zhidong Tang, Qi Liu, Xufeng Kou, Chixiao Chen
2024	—	`conf`	A 28nm 76.25TOPS/W RRAM/SRAM-Collaborative CIM Fine-Tuning Accelerator with RRAM-Endurance/Latency-Aware Weight Allocation for CNN and Transformer. A-SSCC Chen Mu, Zhirui Huang, Hao Jiang, Jie Liao, Bo Jiao, Yuliang Zhou, Haozhe Zhu, Jianguo Yang, Qi Liu, Chixiao Chen
2024	—	`conf`	A 32×32 Flash LiDAR SPAD Sensor with Up-to-1kfps Motional Target Detection by Threshold-adaptive 2D Dynamic Vision. CICC Jingyi Wang, Zhangcheng Huang, Bu Chen, Hongyang Shang, Jiapei Zheng, Hankun Lv, Chixiao Chen, Qi Liu, Ming Liu
2024	J	`jnl`	A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration. Integr. Yinglin Yang, Yunzhengmao Wang, Tengyue Yi, Chixiao Chen, Qi Liu
2024	—	`conf`	A Real-Time Optical-Flow-based SLAM FPGA Accelerator with Inter-Frame Similarity Exploitation and Correlation-Guided Mixed-Precision Flow Update. A-SSCC Mengjie Li, Haozhe Zhu, Yiming Zhang, Siqi He, Qi Liu, Xiaoyang Zeng, Chixiao Chen
2024	A	`conf`	ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test. DATE Hongyi Zhang, Haozhe Zhu, Siqi He, Mengjie Li, Chengchen Wang, Xiankui Xiong, Haidong Tian, Xiaoyang Zeng, Chixiao Chen
2024	A*	`conf`	CAMPER: Exploring the Potential of Content Addressable Memory for 3D Point Cloud Efficient Range Search. DAC Jiapei Zheng, Lizhou Wu, Yutong Su, Jingyi Wang, Zhangcheng Huang, Chixiao Chen, Qi Liu
2024	A*	`conf`	CEDAR: Computing-in-pixel Edge-aware Detection and Reconstruction Architecture for High-resolution 3D Imaging. DAC Bu Chen, Zhangcheng Huang, Qi Zheng, Weiyi Tang, Jingyi Wang, Hankun Lv, Chixiao Chen, Jianlu Wang, Qi Liu
2024	J	`jnl`	FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer. IEEE Trans. Circuits Syst. I Regul. Pap. Bo Jiao, Lei Xu, Xinyu Yu, Haitao Yang, Haozhe Zhu, Yu Wang, Jundong Zhu, Dexin Wen, Lingli Wang, Jun Tao, Chixiao Chen, Yinhe Han, Qi Liu, Ninghui Sun, Ming Liu
2024	A*	`conf`	GauSPU: 3D Gaussian Splatting Processor for Real-Time SLAM Systems. MICRO Lizhou Wu, Haozhe Zhu, Siqi He, Jiapei Zheng, Chixiao Chen, Xiaoyang Zeng
2024	J	`jnl`	HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. IEEE Trans. Very Large Scale Integr. Syst. Shiwei Liu, Chen Mu, Hao Jiang, Yunzhengmao Wang, Jinshan Zhang, Feng Lin, Keji Zhou, Qi Liu, Chixiao Chen
2024	J	`jnl`	Hi-NeRF: A Multicore NeRF Accelerator With Hierarchical Empty Space Skipping for Edge 3-D Rendering. IEEE Trans. Very Large Scale Integr. Syst. Lizhou Wu, Haozhe Zhu, Jiapei Zheng, Mengjie Li, Yinuo Cheng, Qi Liu, Xiaoyang Zeng, Chixiao Chen
2024	J	`jnl`	SLAM-CIM: A Visual SLAM Backend Processor With Dynamic-Range-Driven-Skipping Linear-Solving FP-CIM Macros. IEEE J. Solid State Circuits Mengjie Li, Haozhe Zhu, Siqi He, Hongyi Zhang, Jie Liao, Danfeng Zhai, Chixiao Chen, Qi Liu, Xiaoyang Zeng, Ninghui Sun, Ming Liu
2024	—	`conf`	ST-BPTT: A Memory-efficient BPTT SNN Training Approach through Gradient-Contribution-Driven Time-Step Selection. BioCAS Jiajun Lu, Haozhe Zhu, Xiaoyang Zeng, Chixiao Chen
2024	J	`jnl`	Trident-CIM: A LUT-Based Compute-in-Memory Macro With Trident Read Bit-Line and Partial Product Pruning. IEEE Trans. Circuits Syst. II Express Briefs Haozhe Zhu, Hongyi Zhang, Siqi He, Mengjie Li, Xiaoyang Zeng, Chixiao Chen
2023	C	`conf`	A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. ISCAS Hao Jiang, Jiapei Zheng, Yunzhengmao Wang, Jinshan Zhang, Haozhe Zhu, Liangjian Lyu, Yingping Chen, Chixiao Chen, Qi Liu
2023	C	`conf`	A 10b 1.25GS/s Residue Post-Amplified Pipelined-SAR ADC with Supply-and-Temperature Stabilized Open-Loop Residue Amplifier. ISCAS Xinsheng Wang, Maosong Shi, Peizhe Li, Jianwei Liu, Zhangcheng Huang, Chixiao Chen, Wenning Jiang
2023	J	`jnl`	A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. IEEE J. Solid State Circuits Wenning Jiang, Yan Zhu, Chixiao Chen, Hao Xu, Qi Liu, Ming Liu, Rui Paulo Martins, Chi-Hang Chan
2023	—	`conf`	A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. ISSCC Shiwei Liu, Peizhe Li, Jinshan Zhang, Yunzhengmao Wang, Haozhe Zhu, Wenning Jiang, Shan Tang, Chixiao Chen, Qi Liu, Ming Liu
2023	C	`conf`	A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration. ISCAS Jie Liao, Bo Jiao, Jinshan Zhang, Shiwei Liu, Hao Jiang, Jun Tao, Wenning Jiang, Qi Liu, Lihua Zhang, Haozhe Zhu, Chixiao Chen
2023	—	`conf`	Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation. AICAS Siqi He, Hongyi Zhang, Mengjie Li, Haozhe Zhu, Chixiao Chen, Qi Liu, Xiaoyang Zeng
2023	—	`conf`	TPNoC: An Efficient Topology Reconfigurable NoC Generator. ACM Great Lakes Symposium on VLSI Jiangnan Yu, Fan Yang, Xiaoling Yi, Chixiao Chen, Jun Tao, Dong Xu, Xiankui Xiong, Haitao Yang
2023	A*	`conf`	TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network. DAC Jiapei Zheng, Hao Jiang, Xinkai Nie, Zhangcheng Huang, Chixiao Chen, Qi Liu
2022	J	`jnl`	2022 roadmap on neuromorphic devices and applications research in China. Neuromorph. Comput. Eng. Qing Wan, Changjin Wan, Huaqiang Wu, Yuchao Yang, Xiaohe Huang, Peng Zhou, Lin Chen, Tian-Yu Wang, Yi Li, Kanhao Xue, Yu-Hui He, Xiangshui Miao, Xi Li, Chenchen Xie, Houpeng Chen, Zhitang Song, Hong Wang, Yue Hao, Junyao Zhang, Jia Huang, Zheng Yu Ren, Li Qiang Zhu, Jianyu Du, Chen Ge, Yang Liu, Guanglong Ding, Ye Zhou, Su-Ting Han, Guosheng Wang, Xiao Yu, Bing Chen, Zhufei Chu, Lunyao Wang, Yinshui Xia, Chen Mu, Feng Lin, Chixiao Chen, Bojun Cheng, Yannan Xing, Weitao Zeng, Hong Chen, Lei Yu, Giacomo Indiveri, Ning Qiao
2022	C	`conf`	A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization. ISCAS Xinru Jia, Haozhe Zhu, Yunzheng Wang, Jinshan Zhang, Feng Lin, Xiankui Xiong, Dong Xu, Chixiao Chen, Qi Liu
2022	—	`conf`	A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits. AICAS Chen Mu, Yunzhengmao Wang, Jiapei Zheng, Shiwei Liu, Keji Zhou, Shan Tang, Chixiao Chen, Qi Liu
2022	J	`jnl`	A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. IEEE J. Emerg. Sel. Topics Circuits Syst. Keji Zhou, Xinru Jia, Chenyang Zhao, Xumeng Zhang, Guangjian Wu, Chen Mu, Haozhe Zhu, Yanting Ding, Chixiao Chen, Xiaoyong Xue, Xiaoyang Zeng, Qi Liu
2022	C	`conf`	An Automated Compiler for RISC-V Based DNN Accelerator. ISCAS Zheng Wu, Wuzhen Xie, Xiaoling Yi, Haitao Yang, Ruiyao Pu, Xiankui Xiong, Haidong Yao, Chixiao Chen, Jun Tao, Fan Yang
2022	A	`conf`	CA-SpaceNet: Counterfactual Analysis for 6D Pose Estimation in Space. IROS Shunli Wang, Shuaibing Wang, Bo Jiao, Dingkang Yang, Liuzhen Su, Peng Zhai, Chixiao Chen, Lihua Zhang
2022	J	`jnl`	CA-SpaceNet: Counterfactual Analysis for 6D Pose Estimation in Space. CoRR Shunli Wang, Shuaibing Wang, Bo Jiao, Dingkang Yang, Liuzhen Su, Peng Zhai, Chixiao Chen, Lihua Zhang
2022	—	`conf`	COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. ISSCC Haozhe Zhu, Bo Jiao, Jinshan Zhang, Xinru Jia, Yunzhengmao Wang, Tianchan Guan, Shengcheng Wang, Dimin Niu, Hongzhong Zheng, Chixiao Chen, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Qi Liu, Yuan Xie, Ming Liu
2022	B	`conf`	Curriculum Adversarial Training for Robust Reinforcement Learning. IJCNN Junru Sheng, Peng Zhai, Zhiyan Dong, Xiaoyang Kang, Chixiao Chen, Lihua Zhang
2022	J	`jnl`	Design Challenges of Intrachiplet and Interchiplet Interconnection. IEEE Des. Test Chixiao Chen, Jieming Yin, Yarui Peng, Maurizio Palesi, Wenxu Cao, Letian Huang, Amit Kumar Singh, Haocong Zhi, Xiaohang Wang
2022	J	`jnl`	High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. IEEE Trans. Circuits Syst. I Regul. Pap. Danfeng Zhai, Wenning Jiang, Xinru Jia, Jingchao Lan, Mingqiang Guo, Sai-Weng Sin, Fan Ye, Qi Liu, Junyan Ren, Chixiao Chen
2022	C	`conf`	NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models. ISCAS Xiaoling Yi, Jiangnan Yu, Zheng Wu, Xiankui Xiong, Dong Xu, Chixiao Chen, Jun Tao, Fan Yang
2022	J	`jnl`	TSA-Net: Tube Self-Attention Network for Action Quality Assessment. CoRR Shunli Wang, Dingkang Yang, Peng Zhai, Chixiao Chen, Lihua Zhang
2021	—	`conf`	A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA. ASP-DAC Bo Jiao, Jinshan Zhang, Yuanyuan Xie, Shunli Wang, Haozhe Zhu, Xiaoyang Kang, Zhiyan Dong, Lihua Zhang, Chixiao Chen
2021	J	`jnl`	A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Yuefeng Cao, Shumin Zhang, Tianli Zhang, Yongzhen Chen, Yutong Zhao, Chixiao Chen, Fan Ye, Junyan Ren
2021	—	`conf`	ALPINE: An Agile Processing-in-Memory Macro Compilation Framework. ACM Great Lakes Symposium on VLSI Jinshan Zhang, Bo Jiao, Yunzhengmao Wang, Haozhe Zhu, Lihua Zhang, Chixiao Chen
2021	—	`conf`	Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization. MWSCAS Danfeng Zhai, Peizhe Li, Jiushan Zhang, Chixiao Chen, Fan Ye, Junyan Ren
2021	—	`conf`	Advances in Continuous-time MASH ΔΣ Modulators. ASICON Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, Guoyong Shi, Guoxing Wang
2021	—	`conf`	Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors. ACM Great Lakes Symposium on VLSI Bo Jiao, Haozhe Zhu, Jinshan Zhang, Shunli Wang, Xiaoyang Kang, Lihua Zhang, Mingyu Wang, Chixiao Chen
2021	—	`conf`	Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. ISOCC Danfeng Zhai, Chixiao Chen, Liang Qi, Fan Ye, Junyan Ren
2021	—	`conf`	Self-coupled MASH Delta-Sigma Modulator with Zero Optimization. ISOCC Jingying Zhang, Yang Zhao, Mingyi Chen, Chixiao Chen, Fan Ye, Liang Qi
2021	A*	`conf`	TSA-Net: Tube Self-Attention Network for Action Quality Assessment. ACM Multimedia Shunli Wang, Dingkang Yang, Peng Zhai, Chixiao Chen, Lihua Zhang
2020	J	`jnl`	A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. Integr. Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi
2020	—	`conf`	A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network. APCCAS Min Chen, Yimin Wu, Jingchao Lan, Fan Ye, Chixiao Chen, Junyan Ren
2020	J	`jnl`	A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. Haozhe Zhu, Chixiao Chen, Shiwei Liu, Qiaosha Zou, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Chuanjin Richard Shi
2020	—	`conf`	XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping. AICAS Shiwei Liu, Haozhe Zhu, Chixiao Chen, Lihua Zhang, Chuanjin Richard Shi
2019	—	`conf`	A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. ESSCIRC Yongzhen Chen, Xingchen Shen, Zhekan Ni, Jingchao Lan, Chixiao Chen, Fan Ye, Junyan Ren
2019	—	`conf`	A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time. CICC Aili Wang, Chixiao Chen, Chuanjin Richard Shi
2019	—	`conf`	A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. ASP-DAC Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi
2019	—	`conf`	Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR. ESSCIRC Tianli Zhang, Yuefeng Cao, Shumin Zhang, Chixiao Chen, Fan Ye, Junyan Ren
2019	J	`jnl`	iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric. IEEE J. Emerg. Sel. Topics Circuits Syst. Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, Chuanjin Richard Shi
2018	A*	`conf`	Exploring the programmability for deep learning processors: from architecture to tensorization. DAC Chixiao Chen, Huwan Peng, Xindi Liu, Hongwei Ding, Chuanjin Richard Shi
2018	J	`jnl`	OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Chixiao Chen, Hongwei Ding, Huwan Peng, Haozhe Zhu, Yu Wang, Chuanjin Richard Shi
2018	—	`conf`	iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS. ESSCIRC Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, Chuanjin Richard Shi
2017	J	`jnl`	Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. Aili Wang, Chixiao Chen, Chuanjin Richard Shi
2017	—	`conf`	High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators. MWSCAS Hang Hu, Zemin Feng, Chixiao Chen, Fan Ye, Junyan Ren
2017	—	`conf`	OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators. ESSCIRC Chixiao Chen, Hongwei Ding, Huwan Peng, Haozhe Zhu, Rui Ma, Peiyong Zhang, Xiaolang Yan, Yu Wang, Mingyu Wang, Hao Min, Chuanjin Richard Shi
2016	—	`conf`	A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network. A-SSCC Bingwei Jiang, Chixiao Chen, Junyan Ren, Howard C. Luong
2016	—	`conf`	Transformer-based varactor-less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOS. A-SSCC Xiaolong Liu, Chixiao Chen, Junyan Ren, Howard C. Luong
2015	—	`conf`	100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array. ASICON Jingjing Wang, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren
2015	—	`conf`	A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method. ASICON Zemin Feng, Jingjing Wang, Chixiao Chen, Jun Xu, Junyan Ren
2015	J	`jnl`	A 270-MS/s 6-b SAR ADC with preamplifier sharing and self-locking comparators. IEICE Electron. Express Chixiao Chen, Jixuan Xiang, Jiang Fan, Xu Jun, Ye Fan, Junyan Ren
2015	—	`conf`	A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. ESSCIRC Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren
2015	J	`jnl`	An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators. IEEE Trans. Circuits Syst. II Express Briefs Chixiao Chen, Zemin Feng, Jun Xu, Fan Ye, Junyan Ren
2014	C	`conf`	A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators. ISCAS Guoxian Dai, Chixiao Chen, Shunli Ma, Fan Ye, Junyan Ren
2014	C	`conf`	A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier. ISCAS Chixiao Chen, Zemin Feng, Huabin Chen, Mingshuo Wang, Jun Xu, Fan Ye, Junyan Ren
2013	—	`conf`	A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. ASICON Yongzhen Chen, Chixiao Chen, Qiang Zhang, Fan Ye, Junyan Ren
2013	—	`conf`	A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers. ASICON Yuzhong Xiao, Chixiao Chen, Rui Wei, Fan Jiang, Jun Xu, Junyan Ren
2013	J	`jnl`	A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1. IEEE Trans. Circuits Syst. I Regul. Pap. Zhenyu Wang, Mingshuo Wang, Weiru Gu, Chixiao Chen, Fan Ye, Junyan Ren
2013	—	`conf`	A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator. ASICON Zemin Feng, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren
2013	J	`jnl`	A mixed sample-time error calibration technique in time-interleaved ADCs. IEICE Electron. Express Bei Yu, Chixiao Chen, Fan Ye, Junyan Ren
2013	—	`conf`	Beyond-one-cycle loop delay CT ΔΣ modulators with proper rational NTF synthesis and time-interleaved quantizers. MWSCAS Fan Jiang, Chixiao Chen, Yuzhong Xiao, Jun Xu, Junyan Ren
2012	—	`conf`	A digitally calibrated current-steering DAC with current-splitting array. MWSCAS Long Cheng, Chixiao Chen, Fan Ye, Ning Li, Junyan Ren
2012	—	`conf`	A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation. APCCAS Yiwen Zhang, Xiaoshi Zhu, Chixiao Chen, Fan Ye, Junyan Ren
2012	—	`conf`	An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling. MWSCAS Chixiao Chen, Shengchang Cai, Jialiang Xu, Xiaoshi Zhu, Fan Ye, Junyan Ren
2011	—	`conf`	A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation. A-SSCC Bei Yu, Chixiao Chen, Yu Zhu, Peng Zhang, Yiwen Zhang, Xiaoshi Zhu, Fan Ye, Junyan Ren
2011	—	`conf`	A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application. ASICON Qianqian Ha, Fan Ye, Chixiao Chen, Xiaoshi Zhu, Mingshuo Wang, Yu-Jing Lin, Ning Li, Junyan Ren