Chittaranjan A. Mandal

74 papers A 2B 4C 3Misc 9Journal 24Unranked 32
YearRankTypeTitle / Venue / Authors
2022 J jnl
Translation validation of coloured Petri net models of programs on integers.
Acta Informatica
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Holger Giese
2018 J jnl
Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model.
CoRR
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2018 J jnl
Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning.
CoRR
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2018 J jnl
STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction.
CoRR
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2017 B conf
An Equivalence Checking Framework for Array-Intensive Programs.
ATVA
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
2017 J jnl
Deriving bisimulation relations from path based equivalence checkers.
Formal Aspects Comput.
Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
2017 J jnl
Distributed construction of minimum Connected Dominating Set in wireless sensor network using two-hop information.
Comput. Networks
Jasaswi Prasad Mohanty, Chittaranjan A. Mandal, Chris Reade
2017 B conf
SamaTulyata: An Efficient Path Based Equivalence Checking Tool.
ATVA
Soumyadip Bandyopadhyay, Santonu Sarkar, Dipankar Sarkar, Chittaranjan A. Mandal
2016 Misc conf
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning.
VLSID
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2016 J jnl
A Path Construction Algorithm for Translation Validation Using PRES+ Models.
Parallel Process. Lett.
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Kunal Banerjee, Krishnam Raju Duddu
2016 — conf
An early global routing framework for uniform wire distribution in SoCs.
SoCC
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2016 — conf
An efficient path based equivalence checking for Petri net based models of programs.
ISEC
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal
2016 J jnl
Construction of minimum connected dominating set in wireless sensor networks using pseudo dominating set.
Ad Hoc Networks
Jasaswi Prasad Mohanty, Chittaranjan A. Mandal, Chris Reade, Ariyam Das
2016 B conf
Translation validation of loop and arithmetic transformations in the presence of recurrences.
LCTES
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
2015 — conf
A New Method for Defining Monotone Staircases in VLSI Floorplans.
ISVLSI
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2015 — conf
A Path-based Equivalence Checking Method for Petri Net based Models of Programs.
ICSOFT-EA
Soumyadip Bandyopadhyay, Dipankar Sarkar, Kunal Banerjee, Chittaranjan A. Mandal
2015 C conf
A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs.
SCAM
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
2015 — conf
Determining Equivalence of Expressions: An Automated Evaluator's Perspective.
T4E
K. K. Sharma, Kunal Banerjee, Chittaranjan A. Mandal
2015 — conf
Establishing Equivalence of Expressions: An Automated Evaluator Designer's Perspective.
MIKE
K. K. Sharma, Kunal Banerjee, Chittaranjan A. Mandal
2015 — conf
Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs.
ICSE (2)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal
2015 — conf
Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking.
ISVLSI
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
2015 — conf
Validating SPARK: High Level Synthesis Compiler.
ISVLSI
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal
2014 — conf
A BDD based secure hardware design method to guard against power analysis attacks.
VDAT
Partha De, Kunal Banerjee, Chittaranjan A. Mandal
2014 C conf
Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks.
DSD
Partha De, Kunal Banerjee, Chittaranjan A. Mandal, Debdeep Mukhopadhyay
2014 J jnl
Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
2014 — conf
Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers.
VDAT
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
2014 Misc conf
Global Routing Using Monotone Staircases with Minimal Bends.
VLSID
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2014 J jnl
Verification of Code Motion Techniques Using Value Propagation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
2013 C conf
Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic.
DSD
Partha De, Kunal Banerjee, Chittaranjan A. Mandal, Debdeep Mukhopadhyay
2013 Misc conf
Determining the User Intent Behind Web Search Queries by Learning from Past User Interactions with Search Results.
COMAD
Ariyam Das, Chittaranjan A. Mandal, Chris Reade
2013 — conf
STAIRoute: Global routing using monotone staircase channels.
ISVLSI
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
2013 Misc conf
Verification of KPN Level Transformations.
VLSI Design
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
2013 J jnl
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
2012 — conf
A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts.
VDAT
Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal
2012 J jnl
Formal verification of code motion techniques using data-flow-driven equivalence checking.
ACM Trans. Design Autom. Electr. Syst.
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar
2012 J jnl
POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads.
J. Low Power Electron.
Priyankar Ghosh, Aritra Hazra, Rahul Gonnabhaktula, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan A. Mandal, Krishna Paul
2012 — conf
Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker.
VDAT
Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
2012 — conf
Workload Driven Power Domain Partitioning.
VDAT
Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta, Chittaranjan A. Mandal
2011 J jnl
A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies.
VLSI Design
Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
2011 B conf
An improved greedy construction of minimum connected dominating sets in wireless networks.
WCNC
Ariyam Das, Chittaranjan A. Mandal, Chris Reade, Manish Aasawat
2011 — conf
POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads.
ISED
Priyankar Ghosh, Aritra Hazra, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan A. Mandal, Krishna Paul
2010 — conf
A BDD-Based Design of an Area-Power Efficient Asynchronous Adder.
ISVLSI
Gopal Paul, Rohit Reddy, Chittaranjan A. Mandal, Bhargab B. Bhattacharya
2010 — conf
A BDD-based approach to design power-aware on-line detectors for digital circuits.
SoCC
Gopal Paul, Santosh Biswas, Chittaranjan A. Mandal, Bhargab B. Bhattacharya
2010 J jnl
An automated high-level topology generation procedure for continuous-time SigmaDelta modulator.
Integr.
Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
2010 — conf
Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques.
ISVLSI
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
2010 J jnl
Minimum Connected Dominating Set Using a Collaborative Cover Heuristic for Ad Hoc Sensor Networks.
IEEE Trans. Parallel Distributed Syst.
Rajiv Misra, Chittaranjan A. Mandal
2009 J jnl
Efficient clusterhead rotation
Wirel. Commun. Mob. Comput.
Rajiv Misra, Chittaranjan A. Mandal
2009 — conf
Location Updates of Mobile Node in Wireless Sensor Networks.
MSN
Rajiv Misra, Chittaranjan A. Mandal
2009 J jnl
Rotation of CDS via Connected Domatic Partition in Ad Hoc Sensor Networks.
IEEE Trans. Mob. Comput.
Rajiv Misra, Chittaranjan A. Mandal
2009 Misc conf
Systematic Methodology for High-Level Performance Modeling of Analog Systems.
VLSI Design
Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
2008 J jnl
A Fast Exploration Procedure for Analog High-Level Specification Translation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan A. Mandal, Amit Patra
2007 J jnl
A System for Automatic Evaluation of C Programs: Features and Interfaces.
Int. J. Web Based Learn. Teach. Technol.
Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade
2007 — conf
Automatic Detection of Human Fall in Video.
PReMI
Vinay Vishwakarma, Chittaranjan A. Mandal, Shamik Sural
2007 — conf
ClusterHead Rotation via Domatic Partition in Self-Organizing Sensor Networks.
COMSWARE
Rajiv Misra, Chittaranjan A. Mandal
2007 — conf
Hand-in-hand verification of high-level synthesis.
ACM Great Lakes Symposium on VLSI
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade
2007 — conf
Recipient Specific Electronic Cash - A Scheme for Recipient Specific Yet Anonymous and Tranferable Electronic Cash.
WEBIST (3)
Chittaranjan A. Mandal, Chris Reade
2007 — conf
Register Sharing Verification During Data-Path Synthesis.
ICCTA
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade
2006 — conf
A Formal Verification Method of Scheduling in High-level Synthesis.
ISQED
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
2006 — conf
A System for Automatic Evaluation of Programs for Correctness and Performance.
WEBIST (2)
Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade
2006 — conf
A System for Automatic Evaluation of Programs for Correctness and Performance.
WEBIST (Selected Papers)
Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade
2006 — conf
A formal approach for high level synthesis of linear analog systems.
ACM Great Lakes Symposium on VLSI
Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
2006 — conf
Animating Algorithms over the Web.
WEBIST (2)
Chittaranjan A. Mandal, Chris Reade
2006 A conf
High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count.
DATE
Soumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra
2006 — conf
Verification of Scheduling in High-level Synthesis.
ISVLSI
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
2004 A conf
A New Approach to Timing Analysis Using Event Propagation and Temporal Logic.
DATE
Arijit Mondal, P. P. Chakrabarti, Chittaranjan A. Mandal
2002 — conf
Timing analysis of tree-like RLC circuits.
ISCAS (4)
Bipin Rajendran, Veerbhan Kheterpal, Abhishek Das, Jayanta Majumder, Chittaranjan A. Mandal, P. P. Chakrabarti
2000 Misc conf
A Genetic Algorithm for the Synthesis of Structured Data Paths.
VLSI Design
Chittaranjan A. Mandal, R. M. Zimmer
2000 J jnl
GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths.
IEEE Trans. Very Large Scale Integr. Syst.
Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
1999 J jnl
A design space exploration scheme for data-path synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
1998 J jnl
Complexity of Scheduling in High Level Synthesis.
VLSI Design
Chittaranjan A. Mandal, Partha Pratim Chakrabarti, Sujoy Ghose
1997 Misc conf
Design Space Exploration for Data Path Synthesis.
VLSI Design
Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
1996 Misc conf
Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach.
VLSI Design
Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
1992 Misc conf
Interconnect Optimization Techniques in Data Path Synthesis.
VLSI Design
Chittaranjan A. Mandal, Partha Pratim Chakrabarti, Sujoy Ghose
1992 J jnl
Register-interconnect optimization in data path synthesis.
Microprocess. Microprogramming
Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose