Chirn Chye Boon

68 papers A 1C 9Journal 40Unranked 18

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A 0.6 V, 1.74 mW, 2.9 dB NF Inductorless Wideband LNA in 28-nm CMOS Exploiting Noise Cancellation and Current Reuse. IEEE Trans. Circuits Syst. I Regul. Pap. Zhe Liu, Chirn Chye Boon, Yangtao Dong
2023	—	`conf`	A 2.4dB NF +4.1dBm IIP3 Differential Dual-Feedforward-Based Noise-Cancelling LNTA With Complementary NMOS and PMOS Configuration. ESSCIRC Zhe Liu, Chirn Chye Boon, Yangtao Dong, Kaituo Yang
2023	—	`conf`	A Single-Channel 10GS/s 8b>36.4d8 SNDR Time-Domain ADC Featuring Loop-Unrolled Asynchronous Successive Approximation in 28nm CMOS. ISSCC Oian Chen, Yuan Liang, Chirn Chye Boon, Oing Liu
2023	J	`jnl`	A Single-Channel Voltage-Scalable 8-GS/s 8-b >37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS. IEEE J. Solid State Circuits Qian Chen, Chirn Chye Boon, Qing Liu, Yuan Liang
2022	—	`conf`	A 0.0078mm2 3.4mW Wideband Positive-feedback-Based Noise-Cancelling LNA in 28nm CMOS Exploiting G ISSCC Zhe Liu, Chirn Chye Boon, Chenyang Li, Kaituo Yang, Yangtao Dong, Ting Guo
2022	J	`jnl`	A 0.092-mm IEEE Trans. Circuits Syst. II Express Briefs Zhe Liu, Chirn Chye Boon
2022	J	`jnl`	A 0.6 V 4 GS/s -56.4 dB THD Voltage-to-Time Converter in 28 nm CMOS. IEEE Access Qian Chen, Chirn Chye Boon, Yuan Liang
2022	—	`conf`	A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise Suppression. CICC Yangtao Dong, Chirn Chye Boon, Kaituo Yang, Zhe Liu
2022	—	`conf`	A Hybrid Coupler-First 5GHz Noise-Cancelling Dual-Mode Receiver with +10dBm in-Band IIP3 in Current-Mode and 1.7dB NF in Voltage-Mode. ISSCC Kaituo Yang, Chirn Chye Boon, Zhe Liu, Jiaming Piao, Ting Guo, Yangtao Dong, Chenyang Li, Ao Zhou, Zhijie Yang, Xiaoying Wang, Yufeng Liu
2022	J	`jnl`	An Equivalent-Time Sampling Millimeter-Wave Ultra-Wideband Radar Pulse Digitizer in CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Gibran Limi Jaya, Chirn Chye Boon, Shoushun Chen, Liter Siek
2021	—	`conf`	A 1.75dB-NF 25mW 5GHz Transformer-Based Noise- Cancelling CMOS Receiver Front-End. ISSCC Kaituo Yang, Chirn Chye Boon, Guangyin Feng, Chenyang Li, Zhe Liu, Ting Guo, Xiang Yi, Yangtao Dong, Ao Zhou, Xiaoying Wang
2021	J	`jnl`	A 2.4-6 GHz Broadband GaN Power Amplifier for 802.11ax Application. IEEE Trans. Circuits Syst. I Regul. Pap. Bei Liu, Chirn Chye Boon, Mengda Mao, Pilsoon Choi, Ting Guo
2021	J	`jnl`	A 20-80 MHz Continuously Tunable Gm-C Low-Pass Filter for Ultra-Low Power WBAN Receiver Front-End. IEEE Access Xiaoying Wang, Chirn Chye Boon, Kaituo Yang, Lingshan Kong
2021	J	`jnl`	A Bidirectional Nonlinearly Coupled QVCO With Passive Phase Interpolation for Multiphase Signals Generation. IEEE Trans. Very Large Scale Integr. Syst. Yangtao Dong, Chirn Chye Boon, Xin Ding, Chenyang Li, Zhe Liu
2021	C	`conf`	A Cross-Coupled Pair Regeneration Based dB-Linear Programable Gain Amplifier with THD Enhancement. ISCAS Yangtao Dong, Chirn Chye Boon, Kaituo Yang, Ao Zhou, Xin Ding
2021	J	`jnl`	A Low-Power Quadrature LO Generator With Mutual Power-Supply Rejection Technique. IEEE Access Ao Zhou, Xin Ding, Chirn Chye Boon, Liter Siek, Yuan Liang, Yangtao Dong
2021	J	`jnl`	A Parallel Sliding-IF Receiver Front-End With Sub-2-dB Noise Figure for 5-6-GHz WLAN Carrier Aggregation. IEEE J. Solid State Circuits Kaituo Yang, Xiang Yi, Chirn Chye Boon, Zhipeng Liang, Guangyin Feng, Chenyang Li, Bei Liu
2021	C	`conf`	Millimetre-Wave and Terahertz Antennas and Directional Coupler Enabled by Wafer-Level Packaging Platform with Interposer. ISCAS Yuan Liang, Chirn Chye Boon, Qian Chen, Yangtao Dong
2021	J	`jnl`	Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. IEEE Access Lingshan Kong, Yong Chen, Haohong Yu, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins
2020	—	`conf`	A 0.024-mm MWSCAS Yong Chen, Pui-In Mak, Chirn Chye Boon, Rui Paulo Martins
2020	C	`conf`	A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter. ISCAS Qian Chen, Yuan Liang, Bongjin Kim, Chirn Chye Boon
2020	C	`conf`	A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS. ISCAS Qian Chen, Yuan Liang, Chirn Chye Boon
2020	J	`jnl`	An Inverted Ring Oscillator Noise-Shaping Time-to-Digital Converter With In-Band Noise Reduction and Coherent Noise Cancellation. IEEE Trans. Circuits Syst. I Regul. Pap. Xiang Yi, Zhipeng Liang, Chirn Chye Boon, Guangyin Feng, Fanyi Meng, Kaituo Yang
2020	J	`jnl`	Compact Switched-Capacitor Power Detector With Frequency Compensation in 65-nm CMOS. IEEE Access Chenyang Li, Chirn Chye Boon, Xiang Yi, Zhipeng Liang, Kaituo Yang
2020	J	`jnl`	Design of a Wideband Variable-Gain Amplifier With Self-Compensated Transistor for Accurate dB-Linear Characteristic in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. Lingshan Kong, Hang Liu, Xi Zhu, Chirn Chye Boon, Chenyang Li, Zhe Liu, Kiat Seng Yeo
2020	—	`conf`	Monolithically Integrated GaN+CMOS Logic Circuits Design and Electro-Thermal Analysis for High-Voltage Applications. BCICTS Pilsoon Choi, Bugra Kanargi, Kenneth E. Lee, Chirn Chye Boon, Evelyn Wang, Chuan Seng Tan, Dimitri A. Antoniadis, Eugene A. Fitzgerald
2020	C	`conf`	Multi-Channel FSK Inter/Intra-Chip Communication by Exploiting Field-Confined Slow-Wave Transmission Line. ISCAS Qian Chen, Chirn Chye Boon, Xueyong Zhang, Chenyang Li, Yuan Liang, Zhe Liu, Ting Guo
2019	J	`jnl`	A 0.0071-mm IEEE Trans. Circuits Syst. I Regul. Pap. Yong Chen, Pui-In Mak, Zunsong Yang, Chirn Chye Boon, Rui Paulo Martins
2019	J	`jnl`	A 0.044-mm IEEE Trans. Circuits Syst. II Express Briefs Haohong Yu, Yong Chen, Chirn Chye Boon, Chenyang Li, Pui-In Mak, Rui Paulo Martins
2019	J	`jnl`	A 24/77 GHz Dual-Band Receiver for Automotive Radar Applications. IEEE Access Xiang Yi, Guangyin Feng, Zhipeng Liang, Cheng Wang, Bei Liu, Chenyang Li, Kaituo Yang, Chirn Chye Boon, Quan Xue
2019	—	`conf`	A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS. APCCAS Arya Balachandran, Yong Chen, Chirn Chye Boon
2019	J	`jnl`	A Low-Noise, Positive-Input, Negative-Output Voltage Generator for Low-to-Moderate Driving Capacity Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Devrishi Khanna, Chirn Chye Boon, Pilsoon Choi, Liter Siek, Bei Liu, Chenyang Li
2019	J	`jnl`	Design and Analysis of $D$ -Band On-Chip Modulator and Signal Source Based on Split-Ring Resonator. IEEE Trans. Very Large Scale Integr. Syst. Yuan Liang, Chirn Chye Boon, Chenyang Li, Xiao-Lan Tang, Herman Jalli Ng, Dietmar Kissinger, Yong Wang, Qingfeng Zhang, Hao Yu
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019	—	`conf`	Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. APCCAS Lingshan Kong, Yong Chen, Haohong Yu, Quan Pan, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins
2018	J	`jnl`	A 0.013-mm IEEE Trans. Very Large Scale Integr. Syst. Arya Balachandran, Yong Chen, Chirn Chye Boon
2018	J	`jnl`	A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin. IEEE Trans. Circuits Syst. I Regul. Pap. Yong Chen, Pui-In Mak, Chirn Chye Boon, Rui Paulo Martins
2018	J	`jnl`	A W-Band Switch-Less Dicke Receiver for Millimeter-Wave Imaging in 65 nm CMOS. IEEE Access Guangyin Feng, Xiang Yi, Fanyi Meng, Chirn Chye Boon
2018	J	`jnl`	A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Lingshan Kong, Yong Chen, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins
2018	—	`conf`	D-Band Surface-Wave Modulator and Signal Source with 40 dB Extinction Ratio and 3.7mW Output Power in 65 nm CMOS. ESSCIRC Yuan Liang, Hao Yu, Chirn Chye Boon, Chenyang Li, Dietmar Kissinger, Yong Wang
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017	J	`jnl`	Pole-Converging Intrastage Bandwidth Extension Technique for Wideband Amplifiers. IEEE J. Solid State Circuits Guangyin Feng, Chirn Chye Boon, Fanyi Meng, Xiang Yi, Kaituo Yang, Chenyang Li, Howard C. Luong
2016	—	`conf`	An on-chip integrated III-V / CMOS 125MSps 6-bit SAR ADC. ISIC Sunny Sharma, Siau Ben Chiah, Xing Zhou, Chirn Chye Boon
2015	J	`jnl`	Cell-Based Variable-Gain Amplifiers With Accurate dB-Linear Characteristic in 0.18 µm CMOS Technology. IEEE J. Solid State Circuits Hang Liu, Xi Zhu, Chirn Chye Boon, Xiaofeng He
2014	J	`jnl`	A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology. IEEE J. Solid State Circuits Xiang Yi, Chirn Chye Boon, Hang Liu, Jia-Fu Lin, Wei Meng Lim
2014	A	`conf`	A case for leveraging 802.11p for direct phone-to-phone communications. ISLPED Pilsoon Choi, Jason H. Gao, Nadesh Ramanathan, Mengda Mao, Shipeng Xu, Chirn Chye Boon, Suhaib A. Fahmy, Li-Shiuan Peh
2014	J	`jnl`	Design and Analysis of a 2.4 GHz Hybrid Type Automatic amplitude Control VCO with Forward noise Reduction. J. Circuits Syst. Comput. Y. X. Zhang, Chirn Chye Boon, Kiat Seng Yeo
2013	—	`conf`	A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS. ISSCC Xiang Yi, Chirn Chye Boon, Hang Liu, Jia-Fu Lin, Jian Cheng Ong, Wei Meng Lim
2013	C	`conf`	A low-noise amplifier with continuously-tuned input matching frequency and output resonance frequency. ISCAS Xi Zhu, Chirn Chye Boon, Ayobami Iji, Yichuang Sun, Michael Heimlich
2013	J	`jnl`	Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission. IEEE Trans. Very Large Scale Integr. Syst. Dandan Chen, Kiat Seng Yeo, Xiaomeng Shi, Manh Anh Do, Chirn Chye Boon, Wei Meng Lim
2013	—	`conf`	Design of a fully integrated CMOS dual K- and W-band lumped wilkinson power divider. MWSCAS Nan Huang, Xiang Yi, Chirn Chye Boon, Xiaojin Zhao, Junyi Sun, Guangyin Feng
2012	—	`conf`	A 100 GHz transformer-based varactor-less VCO with 11.2% tuning range in 65nm CMOS technology. ESSCIRC Xiang Yi, Chirn Chye Boon, Jia-Fu Lin, Wei Meng Lim
2012	J	`jnl`	A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. Yung Sern Tan, Kiat Seng Yeo, Chirn Chye Boon, Manh Anh Do
2012	J	`jnl`	A Low-Power Single-Phase Clock Multiband Flexible Divider. IEEE Trans. Very Large Scale Integr. Syst. Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo
2012	J	`jnl`	A low power low phase noise dual-band multiphase VCO. Microelectron. J. Juan Xie, Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo
2012	—	`conf`	Design of quarter-wavelength resonator filters with coupling controllable paths. APCCAS Fanyi Meng, Kaixue Ma, Shanshan Xu, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng Lim, Manh Anh Do
2012	J	`jnl`	Implementations of Signal-Processing Algorithms for OFDM Systems. J. Electr. Comput. Eng. Ming-Der Shieh, Yin-Tsung Hwang, Hanho Lee, Chirn Chye Boon, Zhiyuan Yan
2011	C	`conf`	A 3.1-8 GHz CMOS UWB front-end receiver. ISCAS Ali Meaamar, Chirn Chye Boon, Xiaomeng Shi, Wei Meng Lim, Kiat Seng Yeo, Manh Anh Do
2010	—	`conf`	A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole. VLSI-SoC (Selected Papers) Aaron V. T. Do, Chirn Chye Boon, Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo
2010	C	`conf`	A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole. VLSI-SoC Aaron V. T. Do, Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Alper Cabuk
2010	—	`conf`	A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4. VLSI-SoC (Selected Papers) Manthena Vamshi Krishna, Xuan Jie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do
2010	C	`conf`	A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4. VLSI-SoC Manthena Vamshi Krishna, Juan Xie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do
2010	J	`jnl`	A Wideband Low Power Low-Noise Amplifier in CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Ali Meaamar, Chirn Chye Boon, Kiat Seng Yeo, Manh Anh Do
2010	J	`jnl`	An Energy-Aware CMOS Receiver Front End for Low-Power 2.4-GHz Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Aaron V. T. Do, Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Alper Cabuk
2010	J	`jnl`	Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler. IEEE Trans. Circuits Syst. I Regul. Pap. Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng Lim
2010	J	`jnl`	Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback. IEEE Trans. Very Large Scale Integr. Syst. Zhenghao Lu, Kiat Seng Yeo, Wei Meng Lim, Manh Anh Do, Chirn Chye Boon
2005	J	`jnl`	Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction. IEEE Trans. Circuits Syst. I Regul. Pap. Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Jianguo Ma
2004	J	`jnl`	RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor. IEEE Trans. Circuits Syst. II Express Briefs Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Jianguo Ma, Xiaoling Zhang