Chirag Sudarshan

30 papers A 3C 4Misc 1Journal 11Unranked 11

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Analog in-memory computing attention mechanism for fast and energy-efficient large language models. Nat. Comput. Sci. Nathan Leroux, Paul-Philipp Manea, Chirag Sudarshan, Jan Finkbeiner, Sebastian Siegel, John Paul Strachan, Emre Neftci
2025	J	`jnl`	Efficient Deep Neural Network Training With a Novel 5.3-Bit Block Floating Point Data Format. IEEE Trans. Circuits Syst. Artif. Intell. Mohammad Hassani Sadi, Chirag Sudarshan, Sani R. Nassif, Norbert Wehn
2024	J	`jnl`	Analog In-Memory Computing Attention Mechanism for Fast and Energy-Efficient Large Language Models. CoRR Nathan Leroux, Paul-Philipp Manea, Chirag Sudarshan, Jan Finkbeiner, Sebastian Siegel, John Paul Strachan, Emre Neftci
2024	J	`jnl`	Novel adaptive quantization methodology for 8-bit floating-point DNN training. Des. Autom. Embed. Syst. Mohammad Hassani Sadi, Chirag Sudarshan, Norbert Wehn
2023	—	`conf`	Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories. NANOARCH Paul-Philipp Manea, Chirag Sudarshan, Felix Cüppers, John Paul Strachan
2023	A	`conf`	ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. DATE Gia Bao Thieu, Sven Gesper, Guillermo Payá-Vayá, Christoph Riggers, Oliver Renke, Till Fiedler, Jakob Marten, Tobias Stuckenberg, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart M. Reimann, Rainer Leupers, Michael Beyer, Daniel Köhler, Alisa Jauch, Jan Micha Borrmann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Blüthgen, Christian Sauer
2022	—	`conf`	A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions. SAMOS Chirag Sudarshan, Mohammad Hassani Sadi, Lukas Steiner, Christian Weis, Norbert Wehn
2022	—	`conf`	A Framework for Formal Verification of DRAM Controllers. MEMSYS Lukas Steiner, Chirag Sudarshan, Matthias Jung, Dominik Stoffel, Norbert Wehn
2022	J	`jnl`	A Framework for Formal Verification of DRAM Controllers. CoRR Lukas Steiner, Chirag Sudarshan, Matthias Jung, Dominik Stoffel, Norbert Wehn
2022	J	`jnl`	A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference. IEEE J. Emerg. Sel. Topics Circuits Syst. Chirag Sudarshan, Taha Soliman, Jan Lappas, Christian Weis, Mohammad Hassani Sadi, Matthias Jung, Andre Guntoro, Norbert Wehn
2022	C	`conf`	FeFET versus DRAM based PIM Architectures: A Comparative Study. VLSI-SoC Chirag Sudarshan, Taha Soliman, Thomas Kämpfe, Christian Weis, Norbert Wehn
2022	C	`conf`	Optimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training. ISCAS Chirag Sudarshan, Mohammad Hassani Sadi, Christian Weis, Norbert Wehn
2021	J	`jnl`	A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation. IEEE Trans. Circuits Syst. II Express Briefs Chirag Sudarshan, Lukas Steiner, Matthias Jung, Jan Lappas, Christian Weis, Norbert Wehn
2021	—	`conf`	A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs. ASP-DAC Chirag Sudarshan, Taha Soliman, Cecilia De la Parra, Christian Weis, Leonardo Ecco, Matthias Jung, Norbert Wehn, Andre Guntoro
2021	J	`jnl`	Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks. J. Signal Process. Syst. Vladimir Rybalkin, Chirag Sudarshan, Christian Weis, Jan Lappas, Norbert Wehn, Li Cheng
2020	—	`conf`	A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions. MEMSYS Muhammad Mohsin Ghaffar, Chirag Sudarshan, Christian Weis, Matthias Jung, Norbert Wehn
2020	—	`conf`	Efficient Generation of Application Specific Memory Controllers. MEMSYS Marco V. Natale, Matthias Jung, Kira Kraft, Frederik Lauer, Johannes Feldmann, Chirag Sudarshan, Christian Weis, Sven Oliver Krumke, Norbert Wehn
2020	J	`jnl`	Efficient Hardware Architectures for 1D- and MD-LSTM Networks. J. Signal Process. Syst. Vladimir Rybalkin, Chirag Sudarshan, Christian Weis, Jan Lappas, Norbert Wehn, Li Cheng
2020	—	`conf`	Multi-Valued Physical Unclonable Functions based on Dynamic Random Access Memory. MEMSYS Sven Müelich, Chirag Sudarshan, Christian Weis, Martin Bossert, Robert F. H. Fischer, Norbert Wehn
2020	J	`jnl`	eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. J. Signal Process. Syst. Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn
2019	—	`conf`	A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing. SAMOS Chirag Sudarshan, Jan Lappas, Christian Weis, Deepak M. Mathew, Matthias Jung, Norbert Wehn
2019	C	`conf`	An In-DRAM Neural Network Processing Engine. ISCAS Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung, Norbert Wehn
2019	Misc	`conf`	Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements. REDUNDANCY Sven Müelich, Sebastian Bitzer, Chirag Sudarshan, Christian Weis, Norbert Wehn, Martin Bossert, Robert F. H. Fischer
2019	—	`conf`	Fast validation of DRAM protocols with timed petri nets. MEMSYS Matthias Jung, Kira Kraft, Taha Soliman, Chirag Sudarshan, Christian Weis, Norbert Wehn
2019	J	`jnl`	eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. CoRR Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Syed Mohammad Asad Hassan Jafri, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn
2018	A	`conf`	An analysis on retention error behavior and power consumption of recent DDR4 DRAMs. DATE Deepak M. Mathew, Martin Schultheis, Carl Christian Rheinländer, Chirag Sudarshan, Christian Weis, Norbert Wehn, Matthias Jung
2018	—	`conf`	Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving. MEMSYS Matthias Jung, Sally A. McKee, Chirag Sudarshan, Christoph Dropmann, Christian Weis, Norbert Wehn
2018	—	`conf`	Efficient coding scheme for DDR4 memory subsystems. MEMSYS Kira Kraft, Deepak M. Mathew, Chirag Sudarshan, Matthias Jung, Christian Weis, Norbert Wehn, Florian Longnos
2018	A	`conf`	Improving the error behavior of DRAM by exploiting its Z-channel property. DATE Kira Kraft, Chirag Sudarshan, Deepak M. Mathew, Christian Weis, Norbert Wehn, Matthias Jung
2018	C	`conf`	The Role of Memories in Transprecision Computing. ISCAS Christian Weis, Matthias Jung, Éder F. Zulian, Chirag Sudarshan, Deepak M. Mathew, Norbert Wehn