Chirag Ravishankar

15 papers A 5B 2C 1Misc 2Journal 2Unranked 3

Year	Rank	Type	Title / Venue / Authors
2025	Misc	`conf`	Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox. FCCM Shashwat Shrivastava, Stefan Nikolic, Sun Tanaka, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
2023	A	`conf`	IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. ICCAD Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
2023	A	`conf`	Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. FPGA Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
2023	Misc	`conf`	Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. FCCM Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde
2019	A	`conf`	Xilinx Adaptive Compute Acceleration Platform: Versal FPGA Brian Gaide, Dinesh Gaitonde, Chirag Ravishankar, Trevor Bauer
2018	B	`conf`	Placement Strategies for 2.5D FPGA Fabric Architectures. FPL Chirag Ravishankar, Dinesh Gaitonde, Trevor Bauer
2018	—	`conf`	SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs. FPT Chirag Ravishankar, Henri Fraisse, Dinesh Gaitonde
2012	—	`conf`	Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms. ISQED Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings
2012	A	`conf`	EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only). FPGA Sundaram Ananthanarayanan, Chirag Ravishankar, Siddharth Garg, Andrew A. Kennings
2012	B	`conf`	EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip. FPL Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings
2012	J	`jnl`	FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings
2012	C	`conf`	FPGA power reduction by guarded evaluation considering physical information. VLSI-SoC Chirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson
2012	J	`jnl`	Raising FPGA Logic Density Through Synthesis-Inspired Architecture. IEEE Trans. Very Large Scale Integr. Syst. Jason Helge Anderson, Qiang Wang, Chirag Ravishankar
2011	—	`conf`	Parallel FPGA technology mapping using multi-core architectures. CCECE Andrew A. Kennings, Chirag Ravishankar
2010	A	`conf`	FPGA power reduction by guarded evaluation. FPGA Jason Helge Anderson, Chirag Ravishankar