Chip-Hong Chang

312 papers A* 11A 2B 1C 67Journal 132Unranked 89
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Lightweight PUF-Based Secure Group Communication Scheme for Low Altitude Network With Dynamic Group Membership.
IEEE Trans. Mob. Comput.
Yue Zheng, Harishma Boyapally, Wenye Liu, Yongkui Yang, Chip-Hong Chang
2026 J jnl
High-Fidelity Face Content Recovery via Tamper-Resilient Versatile Watermarking.
CoRR
Peipeng Yu, JinFeng Xie, Chengfu Ou, Xiaoyu Zhou, Jianwei Fei, Yunshu Dai, Zhihua Xia, Chip-Hong Chang
2026 J jnl
SLAPE: Secure Lightweight Authentication for Privacy-Enhanced Federated Learning in Industrial Internet of Things.
IEEE Internet Things J.
Shanyao Ren, Jianwei Liu, Chip-Hong Chang, Hanzhou Wang, Dongyu Li
2025 J jnl
A 0.787 pJ/bit, 25 Mbps True Random Number Generator Based on Analog Chaotic Tent Map.
IEEE Trans. Circuits Syst. II Express Briefs
Yuan Cao, Zheng Wan, Zhao Huang, Chip-Hong Chang
2025 C conf
Accuracy-preserving Layer Normalization Approximations for Efficient Transformer Hardware Accelerators.
ISCAS
Nazim Altar Koca, Anh Tuan Do, Chip-Hong Chang
2025 J jnl
Adversarial Attacks Against Deep Learning-Based Radio Frequency Fingerprint Identification.
CoRR
Jie Ma, Junqing Zhang, Guanxiong Shen, Alan Marshall, Chip-Hong Chang
2025 — conf
BadHMP: Backdoor Attack Against Human Motion Prediction.
AsianHOST
Chaohui Xu, Si Wang, Chip-Hong Chang
2025 J jnl
CHIP: Chameleon Hash-based Irreversible Passport for Robust Deep Model Ownership Verification and Active Usage Control.
CoRR
Chaohui Xu, Qi Cui, Chip-Hong Chang
2025 J jnl
HASSLE: A Self-Supervised Learning Enhanced Hijacking Attack on Vertical Federated Learning.
CoRR
Weiyang He, Chip-Hong Chang
2025 J jnl
HAST: A Hardware-Efficient Spatio-Temporal Correlation Near-Sensor Noise Filter for Dynamic Vision Sensors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pradeep Kumar Gopalakrishnan, Chip-Hong Chang, Arindam Basu
2025 C conf
PUF-based Edge DNN Model IP Protection with Self-obfuscation and Publicly Verifiable Ownership.
ISCAS
Jingdong Jiang, Yue Zheng, Chip-Hong Chang
2025 — conf
Performance Evaluation of Neuromorphic Visual Attention Based on Proto-Objects.
AICAS
Amélie Gruel, Adrien F. Vincent, Chip-Hong Chang, Sylvain Saïghi
2025 A* conf
Red Bleed: A Pragmatic Near-Infrared Presentation Attack on Facial Biometric Authentication Systems.
USENIX Security Symposium
Bowen Hu, Kuo Wang, Chip-Hong Chang
2025 J jnl
Securing Cross-Domain Internet of Drones: An RFF-PUF Allied Authenticated Key Exchange Protocol With Over-the-Air Enrollment.
CoRR
Xuanyu Chen, Yue Zheng, Junqing Zhang, Guanxiong Shen, Chip-Hong Chang
2025 — conf
Spatiotemporal Trigger on Event Data for Backdoor Attack on Spiking Neural Networks.
AICAS
Shengyu Gao, Weiyang He, Chip-Hong Chang, Amélie Gruel, Sylvain Saïghi
2025 A* conf
Unlocking the Capabilities of Large Vision-Language Models for Generalizable and Explainable Deepfake Detection.
ICML
Peipeng Yu, Jianwei Fei, Hui Gao, Xuan Feng, Zhihua Xia, Chip-Hong Chang
2025 J jnl
Unlocking the Capabilities of Vision-Language Models for Generalizable and Explainable Deepfake Detection.
CoRR
Peipeng Yu, Jianwei Fei, Hui Gao, Xuan Feng, Zhihua Xia, Chip-Hong Chang
2024 — conf
A Black-Box Targeted Misclassification Attack on Edge AI with Adversarial Examples Generated from RAW Image Sensor Data.
AsianHOST
Bowen Hu, Weiyang He, Kuo Wang, Chip-Hong Chang
2024 A* conf
ASHES '24: Workshop on Attacks and Solutions in Hardware Security.
CCS
Lejla Batina, Chip-Hong Chang, Ulrich Rührmair, Jakub Szefer
2024 — conf
An In-Sensor PUF Featuring Optical Reconfigurability and Near-100% Hardware Reuse Ratio for Trustworthy Sensing.
VLSI Technology and Circuits
Haibiao Zuo, Xiaoliang Huang, Shiqiao Zhang, Chip-Hong Chang, Xiaojin Zhao
2024 J jnl
An Overview of Trustworthy AI: Advances in IP Protection, Privacy-Preserving Federated Learning, Security Verification, and GAI Safety Alignment.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yue Zheng, Chip-Hong Chang, Shih-Hsu Huang, Pin-Yu Chen, Stjepan Picek
2024 J jnl
BadHMP: Backdoor Attack against Human Motion Prediction.
CoRR
Chaohui Xu, Si Wang, Chip-Hong Chang
2024 J jnl
DFREC: DeepFake Identity Recovery Based on Identity-aware Masked Autoencoder.
CoRR
Peipeng Yu, Hui Gao, Zhitao Huang, Zhihua Xia, Chip-Hong Chang
2024 J jnl
Diffense: Defense Against Backdoor Attacks on Deep Neural Networks With Latent Diffusion.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Bowen Hu, Chip-Hong Chang
2024 — conf
Effect of Line Resistance of Passive Memristive Crossbars on Spiking Neural Network Performance.
AICAS
Pierre Lewden, Adrien F. Vincent, Jean Tomas, Chip-Hong Chang, Sylvain Saïghi
2024 A conf
Efficient Fast Additive Homomorphic Encryption Cryptoprocessor for Privacy-Preserving Federated Learning Aggregation.
DATE
Wenye Liu, Nazim Altar Koca, Chip-Hong Chang
2024 C conf
Exploring Error Correction Circuits on RISC-V based Systems for Space Applications.
ISCAS
Nazim Altar Koca, Chip-Hong Chang, Anh Tuan Do, Vishnu P. Nambiar
2024 — conf
GaitSpike: Event-based Gait Recognition With Spiking Neural Network.
AICAS
Ying Tao, Chip-Hong Chang, Sylvain Saïghi, Shengyu Gao
2024 J jnl
Guest Editorial: Toward Trustworthy AI: Advances in Circuits, Systems, and Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Shih-Hsu Huang, Pin-Yu Chen, Stjepan Picek, Chip-Hong Chang
2024 J jnl
IDEA: An Inverse Domain Expert Adaptation Based Active DNN IP Protection Method.
CoRR
Chaohui Xu, Qi Cui, Jinxin Dong, Weiyang He, Chip-Hong Chang
2024 J jnl
LTE: Lightweight and Time-Efficient Hardware Encoder for Post-Quantum Scheme HQC.
IEEE Comput. Archit. Lett.
Yazheng Tu, Pengzhou He, Chip-Hong Chang, Jiafeng Xie
2024 C conf
Live Demonstration: Man-in-the-Middle Attack on Edge Artificial Intelligence.
ISCAS
Bowen Hu, Weiyang He, Si Wang, Wenye Liu, Chip-Hong Chang
2024 — ed.
Proceedings of the 2024 Workshop on Attacks and Solutions in Hardware Security, ASHES 2024, Salt Lake City, UT, USA, October 14-18, 2024
ASHES@CCS
Chip-Hong Chang, Ulrich Rührmair, Jakub Szefer, Lejla Batina, Francesco Regazzoni
2024 J jnl
SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks.
IEEE Trans. Inf. Forensics Secur.
Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li
2024 J jnl
Security and Functional Safety for AI in Embedded Automotive System - A Tutorial.
IEEE Trans. Circuits Syst. II Express Briefs
Yi Wang, Jing Xiao, Zhengzhe Wei, Yuanjin Zheng, Kea-Tiong Tang, Chip-Hong Chang
2024 A* conf
Steganographic Passport: An Owner and User Verifiable Credential for Deep Model IP Protection Without Retraining.
CVPR
Qi Cui, Ruohan Meng, Chaohui Xu, Chip-Hong Chang
2024 J jnl
Steganographic Passport: An Owner and User Verifiable Credential for Deep Model IP Protection Without Retraining.
CoRR
Qi Cui, Ruohan Meng, Chaohui Xu, Chip-Hong Chang
2023 C conf
A Lightweight PUF-based Secure Group Key Agreement Protocol for Wireless Sensor Networks.
ISCAS
Yue Zheng, Wenye Liu, Chip-Hong Chang
2023 J jnl
A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuan Cao, Wanyi Liu, Yue Zheng, Shuai Chen, Jing Ye, Lei Qian, Chip-Hong Chang
2023 A* conf
ASHES '23: Workshop on Attacks and Solutions in Hardware Security.
CCS
Lejla Batina, Chip-Hong Chang, Domenic Forte, Ulrich Rührmair
2023 — conf
An Empirical Study of the Inherent Resistance of Knowledge Distillation Based Federated Learning to Targeted Poisoning Attacks.
ATS
Weiyang He, Zizhen Liu, Chip-Hong Chang
2023 J jnl
An Imperceptible Data Augmentation Based Blackbox Clean-Label Backdoor Attack on Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chaohui Xu, Wenye Liu, Yue Zheng, Si Wang, Chip-Hong Chang
2023 J jnl
Defense against ML-based Power Side-channel Attacks on DNN Accelerators with Adversarial Attacks.
CoRR
Xiaobei Yan, Chip-Hong Chang, Tianwei Zhang
2023 A conf
Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array.
DATE
Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2023 J jnl
Guest Editorial Special Issue on the Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2022).
IEEE Trans. Circuits Syst. I Regul. Pap.
Chip-Hong Chang, Pingqiang Zhou, Yuan Cao, Qiang Liu
2023 C conf
Hardware-efficient Softmax Approximation for Self-Attention Networks.
ISCAS
Nazim Altar Koca, Anh Tuan Do, Chip-Hong Chang
2023 — conf
MERCURY: An Automated Remote Side-channel Attack to Nvidia Deep Learning Accelerator.
ICFPT
Xiaobei Yan, Xiaoxuan Lou, Guowen Xu, Han Qiu, Shangwei Guo, Chip-Hong Chang, Tianwei Zhang
2023 J jnl
Mercury: An Automated Remote Side-channel Attack to Nvidia Deep Learning Accelerator.
CoRR
Xiaobei Yan, Xiaoxuan Lou, Guowen Xu, Han Qiu, Shangwei Guo, Chip-Hong Chang, Tianwei Zhang
2023 J jnl
PUF-Based Mutual Authentication and Key Exchange Protocol for Peer-to-Peer IoT Applications.
IEEE Trans. Dependable Secur. Comput.
Yue Zheng, Wenye Liu, Chongyan Gu, Chip-Hong Chang
2023 — ed.
Proceedings of the 2023 Workshop on Attacks and Solutions in Hardware Security, ASHES 2023, Copenhagen, Denmark, 30 November 2023
ASHES@CCS
Chip-Hong Chang, Ulrich Rührmair, Lejla Batina, Domenic Forte
2023 J jnl
SPFL: A Self-purified Federated Learning Method Against Poisoning Attacks.
CoRR
Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li
2023 J jnl
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jianan Mu, Yi Ren, Wen Wang, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye, Yuan Cao, Huawei Li, Xiaowei Li
2023 J jnl
The ASHES 2021 special issue at JCEN.
J. Cryptogr. Eng.
Chip-Hong Chang, Stefan Katzenbeisser, Debdeep Mukhopadhyay, Ulrich Rührmair
2023 — conf
White-Box Adversarial Attacks on Deep Learning-Based Radio Frequency Fingerprint Identification.
ICC
Jie Ma, Junqing Zhang, Guanxiong Shen, Alan Marshall, Chip-Hong Chang
2023 J jnl
White-Box Adversarial Attacks on Deep Learning-Based Radio Frequency Fingerprint Identification.
CoRR
Jie Ma, Junqing Zhang, Guanxiong Shen, Alan Marshall, Chip-Hong Chang
2023 — conf
Zero-Shot Text Classification via Self-Supervised Tuning.
ACL (Findings)
Chaoqun Liu, Wenxuan Zhang, Guizhen Chen, Xiaobao Wu, Anh Tuan Luu, Chip-Hong Chang, Lidong Bing
2023 J jnl
Zero-Shot Text Classification via Self-Supervised Tuning.
CoRR
Chaoqun Liu, Wenxuan Zhang, Guizhen Chen, Xiaobao Wu, Anh Tuan Luu, Chip-Hong Chang, Lidong Bing
2022 — conf
A Buyer-traceable DNN Model IP Protection Method Against Piracy and Misappropriation.
AICAS
Si Wang, Chaohui Xu, Yue Zheng, Chip-Hong Chang
2022 J jnl
A DNN Fingerprint for Non-Repudiable Model Ownership Identification and Piracy Detection.
IEEE Trans. Inf. Forensics Secur.
Yue Zheng, Si Wang, Chip-Hong Chang
2022 J jnl
A New Energy-Efficient and High Throughput Two-Phase Multi-Bit per Cycle Ring Oscillator-Based True Random Number Generator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuan Cao, Xiaojin Zhao, Wenhan Zheng, Yue Zheng, Chip-Hong Chang
2022 — conf
A Practical Man-in-the-Middle Attack on Deep Learning Edge Device by Sparse Light Strip Injection into Camera Data Lane.
SOCC
Wenye Liu, Weiyang He, Bowen Hu, Chip-Hong Chang
2022 A* conf
ASHES 2022 - 6th Workshop on Attacks and Solutions in Hardware Security.
CCS
Chip-Hong Chang, Domenic Forte, Debdeep Mukhopadhyay, Ulrich Rührmair
2022 J jnl
An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuan Cao, Yanze Wu, Wen Wang, Xu Lu, Shuai Chen, Jing Ye, Chip-Hong Chang
2022 J jnl
Area, Time and Energy Efficient Multicore Hardware Accelerators for Extended Merkle Signature Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuan Cao, Yanze Wu, Lan Qin, Shuai Chen, Chip-Hong Chang
2022 — conf
Deep Texture-Depth-Based Attention for Face Recognition on IoT Devices.
APCCAS
Yuxin Lin, Wenye Liu, Chip-Hong Chang
2022 — conf
Inconspicuous Data Augmentation Based Backdoor Attack on Deep Neural Networks.
SOCC
Chaohui Xu, Wenye Liu, Yue Zheng, Si Wang, Chip-Hong Chang
2022 — ed.
Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security, ASHES 2022, Los Angeles, CA, USA, 11 November 2022
ASHES@CCS
Chip-Hong Chang, Ulrich Rührmair, Debdeep Mukhopadhyay, Domenic Forte
2022 J jnl
Radio Frequency Fingerprints vs. Physical Unclonable Functions - Are They Twins, Competitors, or Allies?
IEEE Netw.
Junqing Zhang, Chip-Hong Chang, Chongyan Gu, Lajos Hanzo
2022 J jnl
The ASHES 2020 special issue at JCEN.
J. Cryptogr. Eng.
Chip-Hong Chang, Stefan Katzenbeisser, Ulrich Rührmair, Patrick Schaumont
2022 — ed.
VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended Selected Papers
VLSI-SoC (Selected Papers)
Victor Grimblatt, Chip-Hong Chang, Ricardo Reis, Anupam Chattopadhyay, Andrea Calimera
2021 — conf
A Forward Error Compensation Approach for Fault Resilient Deep Neural Network Accelerator Design.
ASHES@CCS
Wenye Liu, Chip-Hong Chang
2021 J jnl
A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chongyan Gu, Chip-Hong Chang, Weiqiang Liu, Shichao Yu, Yale Wang, Máire O'Neill
2021 J jnl
A New Lightweight In Situ Adversarial Sample Detector for Edge Deep Neural Network.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Si Wang, Wenye Liu, Chip-Hong Chang
2021 J jnl
A New PUF Based Lock and Key Solution for Secure In-Field Testing of Cryptographic Chips.
IEEE Trans. Emerg. Top. Comput.
Aijiao Cui, Chip-Hong Chang, Wei Zhou, Yue Zheng
2021 J jnl
A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs.
J. Cryptogr. Eng.
Chongyan Gu, Chip-Hong Chang, Weiqiang Liu, Neil Hanley, Jack Miskelly, Máire O'Neill
2021 — ed.
ASHES@CCS 2021: Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security, Virtual Event, Republic of Korea, 19 November 2021
ASHES@CCS
Chip-Hong Chang, Ulrich Rührmair, Stefan Katzenbeisser, Debdeep Mukhopadhyay
2021 J jnl
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei Hu, Chip-Hong Chang, Anirban Sengupta, Swarup Bhunia, Ryan Kastner, Hai Li
2021 — conf
An Ultra-Low Power 3-T Chaotic Map based True Random Number Generator.
AsianHOST
Lijuan Han, Yuan Cao, Lei Qian, Haodong Xie, Chip-Hong Chang
2021 C conf
Fingerprinting Deep Neural Networks - a DeepFool Approach.
ISCAS
Si Wang, Chip-Hong Chang
2021 J jnl
Hardware Security in Emerging Technologies: Vulnerabilities, Attacks, and Solutions.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Naghmeh Karimi, Kanad Basu, Chip-Hong Chang, Jason M. Fung
2021 J jnl
Identification of FSM State Registers by Analytics of Scan-Dump Data.
IEEE Trans. Inf. Forensics Secur.
Aijiao Cui, Chengkang He, Chip-Hong Chang, Hao Lu
2021 C conf
Live Demonstration: Event-Driven Physical Unclonable Function for Proactive Monitoring System by Dynamic Vision Sensor.
ISCAS
Jian Xian Soo, Yue Zheng, Chip-Hong Chang
2021 C conf
Secure Mutual Authentication and Key-Exchange Protocol between PUF-Embedded IoT Endpoints.
ISCAS
Yue Zheng, Chip-Hong Chang
2021 J jnl
Stealthy and Robust Glitch Injection Attack on Deep Learning Accelerator for Target With Variational Viewpoint.
IEEE Trans. Inf. Forensics Secur.
Wenye Liu, Chip-Hong Chang, Fan Zhang
2021 J jnl
The ASHES 2019 special issue at JCEN.
J. Cryptogr. Eng.
Chip-Hong Chang, Daniel E. Holcomb, Ulrich Rührmair, Patrick Schaumont
2021 J jnl
Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Wenye Liu, Chip-Hong Chang, Xueyang Wang, Chen Liu, Jason M. Fung, Mohammad Ebrahimabadi, Naghmeh Karimi, Xingyu Meng, Kanad Basu
2020 J jnl
A 1036-F
IEEE Trans. Very Large Scale Integr. Syst.
Qiang Zhao, Yiheng Wu, Xiaojin Zhao, Yuan Cao, Chip-Hong Chang
2020 J jnl
A New Polarization Image Demosaicking Algorithm by Exploiting Inter-Channel Correlations With Guided Filtering.
IEEE Trans. Image Process.
Shumin Liu, Jiajia Chen, Yuan Xun, Xiaojin Zhao, Chip-Hong Chang
2020 J jnl
A PUF-Based Data-Device Hash for Tampered Image Detection and Source Camera Identification.
IEEE Trans. Inf. Forensics Secur.
Yue Zheng, Yuan Cao, Chip-Hong Chang
2020 A* conf
ASHES 2020: 4th Workshop on Attacks and Solutions in Hardware Security.
CCS
Chip-Hong Chang, Stefan Katzenbeisser, Ulrich Rührmair, Patrick Schaumont
2020 J jnl
Ed-PUF: Event-Driven Physical Unclonable Function for Camera Authentication in Reactive Monitoring System.
IEEE Trans. Inf. Forensics Secur.
Yue Zheng, Xiaojin Zhao, Takashi Sato, Yuan Cao, Chip-Hong Chang
2020 C conf
Fired Neuron Rate Based Decision Tree for Detection of Adversarial Examples in DNNs.
ISCAS
Si Wang, Wenye Liu, Chip-Hong Chang
2020 A* conf
Imperceptible Misclassification Attack on Deep Learning Accelerator by Glitch Injection.
DAC
Wenye Liu, Chip-Hong Chang, Fan Zhang, Xiaoxuan Lou
2020 — ed.
Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, ASHES@CCS 2020, Virtual Event, USA, November 13, 2020
ASHES@CCS
Chip-Hong Chang, Ulrich Rührmair, Stefan Katzenbeisser, Patrick Schaumont
2020 C conf
Reducing Temperature Induced Unreliability in Sub-Threshold Strong PUFs through Circuit Modeling.
ISCAS
Nimesh Shah, Sumon Kumar Bose, Chip-Hong Chang, Arindam Basu
2019 — conf
A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs.
ASHES@CCS
Chongyan Gu, Chip-Hong Chang, Weiqiang Liu, Neil Hanley, Jack Miskelly, Máire O'Neill
2019 — conf
A Modeling Attack Resistant Deception Technique for Securing PUF based Authentication.
AsianHOST
Chongyan Gu, Chip-Hong Chang, Weiqiang Liu, Shichao Yu, Qingqing Ma, Máire O'Neill
2019 C conf
A Reliable Physical Unclonable Function Based on Differential Charging Capacitors.
ISCAS
Hang Yuan, Wei Guo, Chip-Hong Chang, Yuan Cao, Shaojun Wei, Shouyi Yin, Chenchen Deng, Leibo Liu, Wei Ge, Fan Zhang
2019 A* conf
ASHES 2019: 3rd Workshop on Attacks and Solutions in Hardware Security.
CCS
Chip-Hong Chang, Daniel E. Holcomb, Francesco Regazzoni, Ulrich Rührmair, Patrick Schaumont
2019 J jnl
An Energy-Efficient Current-Starved Inverter Based Strong Physical Unclonable Function With Enhanced Temperature Stability.
IEEE Access
Yuan Cao, Wenhan Zheng, Xiaojin Zhao, Chip-Hong Chang
2019 C conf
An In-Pixel Gain Amplifier Based Event-Driven Physical Unclonable Function for CMOS Dynamic Vision Sensors.
ISCAS
Biyin Wang, Xiaojin Zhao, Yue Zheng, Chip-Hong Chang
2019 C conf
Analysis of Circuit Aging on Accuracy Degradation of Deep Neural Network Accelerator.
ISCAS
Wenye Liu, Chip-Hong Chang
2019 J jnl
Area- and Power-Efficient Nearly-Linear Phase Response IIR Filter by Iterative Convex Optimization.
IEEE Access
Gelei Deng, Jiajia Chen, Jiaxuan Zhang, Chip-Hong Chang
2019 — conf
Detecting Adversarial Examples for Deep Neural Networks via Layer Directed Discriminative Noise Injection.
AsianHOST
Si Wang, Wenye Liu, Chip-Hong Chang
2019 J jnl
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019 J jnl
Emerging Attacks and Solutions for Secure Hardware in the Internet of Things.
IEEE Trans. Dependable Secur. Comput.
Chip-Hong Chang, Marten van Dijk, Ulrich Rührmair, Mark Tehranipoor
2019 C conf
High-Speed True Random Number Generator Based on Differential Current Starved Ring Oscillators with Improved Thermal Stability.
ISCAS
Kai Wang, Yuan Cao, Chip-Hong Chang, Xiaoli Ji
2019 — conf
Identification of State Registers of FSM Through Full Scan by Data Analytics.
AsianHOST
Chengkang He, Aijiao Cui, Chip-Hong Chang
2019 — ed.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, ASHES@CCS 2019, London, UK, November 15, 2019.
ASHES@CCS
Chip-Hong Chang, Ulrich Rührmair, Daniel E. Holcomb, Patrick Schaumont
2019 J jnl
Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response.
IEEE Trans. Inf. Forensics Secur.
Siarhei S. Zalivaka, Alexander A. Ivaniuk, Chip-Hong Chang
2019 J jnl
UDhashing: Physical Unclonable Function-Based User-Device Hash for Endpoint Authentication.
IEEE Trans. Ind. Electron.
Yue Zheng, Yuan Cao, Chip-Hong Chang
2019 — conf
Vulnerability Analysis on Noise-Injection Based Hardware Attack on Deep Neural Networks.
AsianHOST
Wenye Liu, Si Wang, Chip-Hong Chang
2018 — conf
A Current Comparator Based Physical Unclonable Function with High Reliability and Energy Efficiency.
DSP
Qiang Zhao, Yuan Cao, Xiaojin Zhao, Chip-Hong Chang
2018 B conf
A Fully Digital Physical Unclonable Function Based Temperature Sensor for Secure Remote Sensing.
ICCCN
Yuan Cao, Yunyi Guo, Benyu Liu, Wei Ge, Min Zhu, Chip-Hong Chang
2018 J jnl
A Low Power Diode-Clamped Inverter-Based Strong Physical Unclonable Function for Robust and Lightweight Authentication.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuan Cao, Chao Qun Liu, Chip-Hong Chang
2018 J jnl
A New Accurate and Fast Homography Computation Algorithm for Sports and Traffic Video Analysis.
IEEE Trans. Circuits Syst. Video Technol.
Shumin Liu, Jiajia Chen, Chip-Hong Chang, Ye Ai
2018 C conf
A Sub-pico Joules Per Bit Robust Physical Unclonable Function Based on Subthreshold Voltage References.
ISCAS
Yuan Cao, Chip-Hong Chang, Wenhan Zheng, Xiaojin Zhao
2018 A* conf
ASHES 2018- Workshop on Attacks and Solutions in Hardware Security.
CCS
Chip-Hong Chang, Jorge Guajardo, Daniel E. Holcomb, Francesco Regazzoni, Ulrich Rührmair
2018 C conf
Active IC Metering of Digital Signal Processing Subsystem with Two-Tier Activation for Secure Split Test.
ISCAS
Sumedh Somnath Dhabu, Yue Zheng, Wenye Liu, Chip-Hong Chang
2018 J jnl
Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zheng Wang, Yi Chen, Aakash Patil, Jayasanker Jayabalan, Xueyong Zhang, Chip-Hong Chang, Arindam Basu
2018 C conf
Facial biohashing based user-device physical unclonable function for bring your own device security.
ICCE
Yue Zheng, Yuan Cao, Chip-Hong Chang
2018 J jnl
New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jiajia Chen, Chip-Hong Chang, Yujia Wang, Juan Zhao, Susanto Rahardja
2018 — ed.
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, ASHES@CCS 2018, Toronto, ON, Canada, October 19, 2018
ASHES@CCS
Chip-Hong Chang, Ulrich Rührmair, Daniel E. Holcomb, Jorge Guajardo
2018 C conf
Securing IoT Monitoring Device using PUF and Physical Layer Authentication.
ISCAS
Yue Zheng, Sumedh Somnath Dhabu, Chip-Hong Chang
2018 J jnl
Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiajia Chen, Chip-Hong Chang, Jiatao Ding, Rui Qiao, Mathias Faust
2018 — conf
Towards Ideal Lattice-Based Cryptography on ASIC: A Custom Implementation of Number Theoretic Transform.
DSP
Truong Phu Truan Ho, Chip-Hong Chang
2017 C conf
20 Years of research on intellectual property protection.
ISCAS
Miodrag Potkonjak, Gang Qu, Farinaz Koushanfar, Chip-Hong Chang
2017 J jnl
A New Cost-Aware Sensitivity-Driven Algorithm for the Design of FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiajia Chen, Jinghong Tan, Chip-Hong Chang, Feng Feng
2017 J jnl
A Scaling-Assisted Signed Integer Comparator for the Balanced Five-Moduli Set RNS 2
IEEE Trans. Very Large Scale Integr. Syst.
Sachin Kumar, Chip-Hong Chang
2017 C conf
A new watermarking scheme on scan chain ordering for hard IP protection.
ISCAS
Xiaonan Huang, Aijiao Cui, Chip-Hong Chang
2017 C conf
A new write-contention based dual-port SRAM PUF with multiple response bits per cell.
ISCAS
Chao Qun Liu, Yue Zheng, Chip-Hong Chang
2017 — conf
A novel scheme for information hiding at physical layer of wireless communications.
ISOCC
Sumedh Dhabu, Chip-Hong Chang
2017 J jnl
ACRO-PUF: A Low-power, Reliable and Aging-Resilient Current Starved Inverter-Based Ring Oscillator Physical Unclonable Function.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chao Qun Liu, Yuan Cao, Chip-Hong Chang
2017 A* conf
ASHES 2017: Workshop on Attacks and Solutions in Hardware Security.
CCS
Chip-Hong Chang, Marten van Dijk, Farinaz Koushanfar, Ulrich Rührmair, Mark Tehranipoor
2017 — conf
An energy-efficient true random number generator based on current starved ring oscillators.
AsianHOST
Yuan Cao, Chip-Hong Chang, Yue Zheng, Xiaojin Zhao
2017 C conf
Current mirror array: A novel lightweight strong PUF topology with enhanced reliability.
ISCAS
Zheng Wang, Yi Chen, Aakash Patil, Chip-Hong Chang, Arindam Basu
2017 J jnl
Editorial.
IEEE Trans. Very Large Scale Integr. Syst.
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017 — conf
FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliability.
ISQED
Siarhei S. Zalivaka, Alexander A. Ivaniuk, Chip-Hong Chang
2017 C conf
Low-cost fortification of arbiter PUF against modeling attack.
ISCAS
Siarhei S. Zalivaka, Alexander A. Ivaniuk, Chip-Hong Chang
2017 J jnl
New Algorithm for Signed Integer Comparison in {2
IEEE Trans. Circuits Syst. I Regul. Pap.
Sachin Kumar, Chip-Hong Chang, Thian Fatt Tay
2017 — ed.
Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security, ASHES@CCS 2017, Dallas, TX, USA, November 3, 2017
ASHES@CCS
Chip-Hong Chang, Ulrich Rührmair, Wei Zhang
2017 J jnl
Static and Dynamic Obfuscations of Scan Data Against Scan-Based Side-Channel Attacks.
IEEE Trans. Inf. Forensics Secur.
Aijiao Cui, Yanhui Luo, Chip-Hong Chang
2016 J jnl
A New Fast and Area-Efficient Adder-Based Sign Detector for RNS {2
IEEE Trans. Very Large Scale Integr. Syst.
Sachin Kumar, Chip-Hong Chang
2016 J jnl
A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jiatao Ding, Jiajia Chen, Chip-Hong Chang
2016 J jnl
A Non-Iterative Multiple Residue Digit Error Detection and Correction Algorithm in RRNS.
IEEE Trans. Computers
Thian Fatt Tay, Chip-Hong Chang
2016 C conf
A VLSI-efficient signed magnitude comparator for { 2n-1, 2n, 2n +2n+1-1} RNS.
ISCAS
Sachin Kumar, Chip-Hong Chang
2016 C conf
A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks.
ISCAS
Govind Narasimman, Subhrajit Roy, Xuanyao Fong, Kaushik Roy, Chip-Hong Chang, Arindam Basu
2016 — conf
A new event-driven Dynamic Vision Sensor based Physical Unclonable Function for camera authentication in reactive monitoring system.
AsianHOST
Yue Zheng, Yuan Cao, Chip-Hong Chang
2016 — conf
A new scheme for secret-hiding in DSP circuits.
ISOCC
Sumedh Dhabu, Chip-Hong Chang
2016 — conf
Accelerating residue-to-binary conversion of very high cardinality moduli set for fully homomorphic encryption.
APCCAS
Truong Phu Truan Ho, Chip-Hong Chang
2016 J jnl
DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory.
IEEE Trans. Inf. Forensics Secur.
Yuhao Wang, Leibin Ni, Chip-Hong Chang, Hao Yu
2016 J jnl
Editorial.
J. Circuits Syst. Comput.
Chip-Hong Chang, Tae-Hyoung Kim, Hao Yu
2016 J jnl
Erratum to "Efficient VLSI Implementation of 2
IEEE Trans. Very Large Scale Integr. Syst.
Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low
2016 J jnl
Hypergraph Based Minimum Arborescence Algorithm for the Optimization and Reoptimization of Multiple Constant Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Feng Feng, Jiajia Chen, Chip-Hong Chang
2016 — conf
Low-power, lightweight and reliability-enhanced current starved inverter based RO PUFs.
APCCAS
Chao Qun Liu, Yuan Cao, Chip-Hong Chang
2016 — conf
Multi-valued Arbiters for quality enhancement of PUF responses on FPGA implementation.
ASP-DAC
Siarhei S. Zalivaka, Alexander V. Puchkov, Vladimir P. Klybik, Alexander A. Ivaniuk, Chip-Hong Chang
2016 — conf
Using image sensor PUF as root of trust for birthmarking of perceptual image hash.
AsianHOST
Yuan Cao, Le Zhang, Chip-Hong Chang
2015 J jnl
A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuan Cao, Le Zhang, Chip-Hong Chang, Shoushun Chen
2015 — conf
A high-speed and area-efficient sign detector for three moduli set RNS {2n, 2n-1, 2n+1}.
ASICON
Sachin Kumar, Chip-Hong Chang
2015 C conf
A new unified modular adder/subtractor for arbitrary moduli.
ISCAS
Thian Fatt Tay, Chip-Hong Chang
2015 J jnl
Base Transformation With Injective Residue Mapping for Dynamic Range Reduction in RNS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Thian Fatt Tay, Chip-Hong Chang, Leonel Sousa
2015 J jnl
CMOS Image Sensor Based Physical Unclonable Function for Coherent Sensor-Level Authentication.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuan Cao, Le Zhang, Siarhei S. Zalivaka, Chip-Hong Chang, Shoushun Chen
2015 J jnl
Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction.
IEEE Trans. Computers
Linfeng Chen, Aijiao Cui, Chip-Hong Chang
2015 — conf
Efficient structural adder pipelining in transposed form FIR filters.
DSP
Mathias Faust, Martin Kumm, Chip-Hong Chang, Peter Zipf
2015 J jnl
Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell.
IEEE Trans. Inf. Forensics Secur.
Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy
2015 J jnl
Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiajia Chen, Chip-Hong Chang, Feng Feng, Weiao Ding, Jiatao Ding
2015 J jnl
Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy
2015 C conf
Public key protocol for usage-based licensing of FPGA IP cores.
ISCAS
Li Zhang, Chip-Hong Chang
2015 C conf
Statistical analysis and design of 6T SRAM cell for physical unclonable function with dual application modes.
ISCAS
Le Zhang, Chip-Hong Chang, Zhi-Hui Kong, Chao Qun Liu
2014 J jnl
A 0.7 V low-power fully programmable Gaussian function generator for brain-inspired Gaussian correlation associative memory.
Neurocomputing
Fei Li, Chip-Hong Chang, Arindam Basu, Liter Siek
2014 J jnl
A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual Property Protection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chip-Hong Chang, Li Zhang
2014 J jnl
A Cluster-Based Distributed Active Current Sensing Circuit for Hardware Trojan Detection.
IEEE Trans. Inf. Forensics Secur.
Yuan Cao, Chip-Hong Chang, Shoushun Chen
2014 J jnl
A Pragmatic Per-Device Licensing Scheme for Hardware IP Cores on SRAM-Based FPGAs.
IEEE Trans. Inf. Forensics Secur.
Li Zhang, Chip-Hong Chang
2014 — conf
A modular design of elliptic-curve point multiplication for resource constrained devices.
ISIC
Wei Wei, Li Zhang, Chip-Hong Chang
2014 C conf
A new algorithm for single residue digit error correction in Redundant Residue Number System.
ISCAS
Thian Fatt Tay, Chip-Hong Chang
2014 C conf
Area-efficient and fast sign detection for four-moduli set RNS {2
ISCAS
Chip-Hong Chang, Sachin Kumar
2014 — conf
CMOS image sensor based physical unclonable function for smart phone security applications.
ISIC
Yuan Cao, Siarhei S. Zalivaka, Le Zhang, Chip-Hong Chang, Shoushun Chen
2014 C conf
Design of programmable FIR filters using Canonical Double Based Number Representation.
ISCAS
Jiajia Chen, Chip-Hong Chang
2014 J jnl
Exploiting Process Variations and Programming Sensitivity of Phase Change Memory for Reconfigurable Physical Unclonable Functions.
IEEE Trans. Inf. Forensics Secur.
Le Zhang, Zhi-Hui Kong, Chip-Hong Chang, Alessandro Cabrini, Guido Torelli
2014 — conf
Hardware Trojan detection with linear regression based gate-level characterization.
APCCAS
Li Zhang, Chip-Hong Chang
2014 C conf
Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM.
ISCAS
Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy
2014 — conf
Leakage-resilient memory-based physical unclonable function using phase change material.
ICCST
Le Zhang, Chip-Hong Chang, Alessandro Cabrini, Guido Torelli, Zhi-Hui Kong
2014 — conf
New algorithm for signed integer comparison in four-moduli superset {2
APCCAS
Thian Fatt Tay, Chip-Hong Chang
2014 — conf
Obfuscation and watermarking of FPGA designs based on constant value generators.
ISIC
Vladimir V. Sergeichik, Alexander A. Ivaniuk, Chip-Hong Chang
2013 J jnl
A New Approach to the Design of Efficient Residue Generators for Arbitrary Moduli.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jeremy Yung Shern Low, Chip-Hong Chang
2013 C conf
A signed integer programmable power-of-two scaler for {2
ISCAS
Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
2013 J jnl
An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits.
Integr.
Hanhua Qian, Chip-Hong Chang, Hao Yu
2013 C conf
Cluster-based distributed active current timer for hardware Trojan detection.
ISCAS
Yuan Cao, Chip-Hong Chang, Shoushun Chen
2013 J jnl
Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n}, 2^{n}+1\}}$.
IEEE Trans. Very Large Scale Integr. Syst.
Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low
2013 C conf
Microchannel splitting and scaling for thermal balancing of liquid-cooled 3DIC.
ISCAS
Hanhua Qian, Chip-Hong Chang
2013 C conf
PCKGen: A Phase Change Memory based cryptographic key generator.
ISCAS
Le Zhang, Zhi-Hui Kong, Chip-Hong Chang
2013 J jnl
Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ramya Muralidharan, Chip-Hong Chang
2013 — conf
Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects.
ASP-DAC
Hanhua Qian, Hao Liang, Chip-Hong Chang, Wei Zhang, Hao Yu
2012 J jnl
A VLSI Efficient Programmable Power-of-Two Scaler for 2
IEEE Trans. Circuits Syst. I Regul. Pap.
Jeremy Yung Shern Low, Chip-Hong Chang
2012 — conf
A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion.
APCCAS
Howard Tang, Joshua Yung Lih Low, Jeremy Yung Shern Low, Liter Siek, Ching-Chuen Jong, Chip-Hong Chang
2012 C conf
A fast and compact circuit for integer square root computation based on Mitchell logarithmic method.
ISCAS
Joshua Yung Lih Low, Ching-Chuen Jong, Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
2012 — conf
A post-processing scan-chain watermarking scheme for VLSI intellectual property protection.
APCCAS
Aijiao Cui, Chip-Hong Chang
2012 — conf
A unified {2
APCCAS
Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
2012 J jnl
An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap.
Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang
2012 J jnl
Area-Power Efficient Modulo 2
IEEE Trans. Circuits Syst. I Regul. Pap.
Ramya Muralidharan, Chip-Hong Chang
2012 J jnl
Dynamical Systems Guided Design and Analysis of Silicon Oscillators for Central Pattern Generators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fei Li, Arindam Basu, Chip-Hong Chang, Avis H. Cohen
2012 J jnl
Foreword.
J. Circuits Syst. Comput.
Pak Kwong Chan, Chip-Hong Chang, Kiat Seng Yeo
2012 J jnl
Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011).
IEEE Trans. Circuits Syst. I Regul. Pap.
Chip-Hong Chang, Howard C. Luong, Shanthi Pavan
2012 C conf
Pipelined adder graph optimization for high speed multiple constant multiplication.
ISCAS
Martin Kumm, Peter Zipf, Mathias Faust, Chip-Hong Chang
2012 C conf
State encoding watermarking for field authentication of sequential circuit intellectual property.
ISCAS
Li Zhang, Chip-Hong Chang
2011 J jnl
A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters.
IEEE Trans. Very Large Scale Integr. Syst.
Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang
2011 J jnl
A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar, Amr Talaat Abdel-Hamid
2011 C conf
A hybrid watermarking scheme for sequential functions.
ISCAS
Aijiao Cui, Chip-Hong Chang, Li Zhang
2011 C conf
A new RNS scaler for {2
ISCAS
Jeremy Yung Shern Low, Chip-Hong Chang
2011 C conf
A simple radix-4 Booth encoded modulo 2
ISCAS
Ramya Muralidharan, Chip-Hong Chang
2011 J jnl
Bayesian Separation With Sparsity Promotion in Perceptual Wavelet Domain for Speech Enhancement and Hybrid Speech Recognition.
IEEE Trans. Syst. Man Cybern. Part A
Yu Shao, Chip-Hong Chang
2011 C conf
Bit-parallel Multiple Constant Multiplication using Look-Up Tables on FPGA.
ISCAS
Mathias Faust, Chip-Hong Chang
2011 J jnl
Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling.
J. Low Power Electron.
Hanhua Qian, Xiwei Huang, Hao Yu, Chip-Hong Chang
2011 — conf
Low error bit width reduction for structural adders of FIR filters.
ECCTD
Mathias Faust, Chip-Hong Chang
2011 J jnl
Radix-8 Booth Encoded Modulo 2
IEEE Trans. Circuits Syst. I Regul. Pap.
Ramya Muralidharan, Chip-Hong Chang
2011 J jnl
Sign-Extension Avoidance and Word-Length Optimization by Positive-Offset Representation for FIR Filter Design.
IEEE Trans. Circuits Syst. II Express Briefs
Ruimin Huang, Chip-Hong Chang, Mathias Faust, Niklas Lotze, Yiannos Manoli
2011 J jnl
Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set 2
IEEE Trans. Circuits Syst. I Regul. Pap.
Chip-Hong Chang, Jeremy Yung Shern Low
2010 J jnl
A Low Error and High Performance Multiplexer-Based Truncated Multiplier.
IEEE Trans. Very Large Scale Integr. Syst.
Chip-Hong Chang, Ravi Kumar Satzoda
2010 C conf
A novel counter-based low complexity inner-product architecture for high speed inputs.
ISCAS
Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang, Jeremy Yung Shern Low
2010 C conf
Fast hard multiple generators for radix-8 Booth encoded modulo 2
ISCAS
Ramya Muralidharan, Chip-Hong Chang
2010 C conf
Minimal Logic Depth adder tree optimization for Multiple Constant Multiplication.
ISCAS
Mathias Faust, Chip-Hong Chang
2010 J jnl
On "A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chip-Hong Chang, Mathias Faust
2010 — conf
Real-time thermal management of 3D multi-core system with fine-grained cooling control.
3DIC
Hanhua Qian, Xiwei Huang, Hao Yu, Chip-Hong Chang
2010 J jnl
Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chip-Hong Chang, Aijiao Cui
2009 C conf
A Compact Current Mode Neuron Circuit with Gaussian Taper Learning Capability.
ISCAS
Fei Li, Chip-Hong Chang, Liter Siek
2009 J jnl
A New Redundant Binary Booth Encoding for Fast 2
IEEE Trans. Circuits Syst. I Regul. Pap.
Yajuan He, Chip-Hong Chang
2009 C conf
An Improved Publicly Detectable Watermarking Scheme based on Scan Chain Ordering.
ISCAS
Aijiao Cui, Chip-Hong Chang
2009 C conf
Fixed and Variable Multi-modulus Squarer Architectures for Triple Moduli base of RNS.
ISCAS
Ramya Muralidharan, Chip-Hong Chang
2009 J jnl
High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jiajia Chen, Chip-Hong Chang
2009 C conf
New Power Index Model for Switching Power Analysis from Adder Graph of FIR filter.
ISCAS
Jiajia Chen, Chip-Hong Chang, Hanhua Qian
2009 C conf
Optimization of Structural Adders in Fixed Coefficient Transposed Direct Form FIR Filters.
ISCAS
Mathias Faust, Chip-Hong Chang
2009 C conf
Time-multiplexed Data Flow Graph for the Design of Configurable Multiplier Block.
ISCAS
Jiajia Chen, Chip-Hong Chang, Ching-Chuen Jong
2008 J jnl
A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yajuan He, Chip-Hong Chang
2008 — conf
A low complexity modulo 2
APCCAS
Ramya Muralidharan, Chip-Hong Chang, Ching-Chuen Jong
2008 J jnl
Contention Resolution - A New Approach to Versatile Subexpressions Sharing in Multiple Constant Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
2008 — conf
High-speed and low-power serial accumulator for serial/parallel multiplier.
APCCAS
Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang
2008 J jnl
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar
2008 J jnl
Information Theoretic Approach to Complexity Reduction of FIR Filter Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chip-Hong Chang, Jiajia Chen, Achutavarrier Prasad Vinod
2008 C conf
Intellectual property authentication by watermarking scan chain in design-for-testability flow.
ISCAS
Aijiao Cui, Chip-Hong Chang
2008 C conf
Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2
ISCAS
Ravi Kumar Satzoda, Ramya Muralidharan, Chip-Hong Chang
2007 J jnl
A Generalized Time-Frequency Subtraction Method for Robust Speech Enhancement Based on Wavelet Filter Banks Modeling of Human Auditory System.
IEEE Trans. Syst. Man Cybern. Part B
Yu Shao, Chip-Hong Chang
2007 J jnl
A Residue-to-Binary Converter for a New Five-Moduli Set.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan
2007 J jnl
Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
2007 J jnl
Hamming weight pyramid - A new insight into canonical signed digit representation and its applications.
Comput. Electr. Eng.
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
2007 J jnl
Low-power differential coefficients-based FIR filters using hardware-optimised multipliers.
IET Circuits Devices Syst.
A. Prasad Vinod, Ankita Singla, Chip-Hong Chang
2007 C conf
Watermarking for IP Protection through Template Substitution at Logic Synthesis Level.
ISCAS
Aijiao Cui, Chip-Hong Chang
2006 — conf
A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters.
APCCAS
Uwe Meyer-Bäse, Jiajia Chen, Chip-Hong Chang, Andrew G. Dempster
2006 C conf
A Kalman filter based on wavelet filter-bank and psychoacoustic modeling for speech enhancement.
ISCAS
Yu Shao, Chip-Hong Chang
2006 — conf
A Reconfigurable Multi-Modulus Modulo Multiplier.
APCCAS
Shibu Menon, Chip-Hong Chang
2006 C conf
A fast kernel for unifying GF(p) and GF(2
ISCAS
Ravi Kumar Satzoda, Chip-Hong Chang
2006 C conf
A generalized perceptual time-frequency subtraction method for speech enhancement.
ISCAS
Yu Shao, Chip-Hong Chang
2006 C conf
A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier.
ISCAS
Yajuan He, Chip-Hong Chang
2006 C conf
A new integrated approach to the design of low-complexity FIR filters.
ISCAS
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
2006 C conf
A novel hybrid neuro-wavelet system for robust speech recognition.
ISCAS
Yu Shao, Chip-Hong Chang
2006 — conf
Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics.
APCCAS
Jiajia Chen, Chip-Hong Chang, A. Prasad Vinod
2006 C conf
Improved differential coefficients-based low power FIR filters. Part I. Fundamentals.
ISCAS
A. Prasad Vinod, Ankita Singla, Chip-Hong Chang
2006 — conf
Kernel Extraction for Watermarking Combinational Logic Networks.
APCCAS
Aijiao Cui, Chip-Hong Chang
2006 — conf
Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm.
APCCAS
A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla
2006 — conf
Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis.
APCCAS
A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla
2006 C conf
Maximum likelihood disjunctive decomposition to reduced multirooted DAG for FIR filter design.
ISCAS
Chip-Hong Chang, Jiajia Chen, A. Prasad Vinod
2006 C conf
Stego-signature at logic synthesis level for digital design IP protection.
ISCAS
Aijiao Cui, Chip-Hong Chang
2005 — conf
A configurable dual moduli multi-operand modulo adder.
ISCAS (2)
Chip-Hong Chang, Shibu Menon, Bin Cao, Thambipillai Srikanthan
2005 — conf
A new design method to modulo 2
ISCAS (1)
Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang
2005 — conf
A new formulation of fast diminished-one multioperand modulo 2
ISCAS (1)
Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan
2005 — conf
A novel covalent redundant binary Booth encoder.
ISCAS (1)
Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy
2005 — conf
A novel multiplexer based truncated array multiplier.
ISCAS (1)
Chip-Hong Chang, Ravi Kumar Satzoda, Swaminathan Sekar
2005 J jnl
A review of 0.18-μm full adder performances for tree structured arithmetic circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang
2005 — conf
A versatile speech enhancement system based on perceptual wavelet denoising.
ISCAS (2)
Yu Shao, Chip-Hong Chang
2005 — ed.
Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings
Asia-Pacific Computer Systems Architecture Conference
Thambipillai Srikanthan, Jingling Xue, Chip-Hong Chang
2005 J jnl
An Ultra Low-power Current-mode Sense Amplifier for Sram Applications.
J. Circuits Syst. Comput.
Zhi-Hui Kong, Kiat Seng Yeo, Chip-Hong Chang
2005 — conf
An area efficient 64-bit square root carry-select adder for low power applications.
ISCAS (4)
Yajuan He, Chip-Hong Chang, Jiangmin Gu
2005 J jnl
Contention resolution algorithm for common subexpression elimination in digital filter design.
IEEE Trans. Circuits Syst. II Express Briefs
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
2005 J jnl
Fuzzy-ART based adaptive digital watermarking scheme.
IEEE Trans. Circuits Syst. Video Technol.
Chip-Hong Chang, Zhi Ye, Mingyan Zhang
2005 — conf
I
ISCAS (2)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
2005 J jnl
New adaptive color quantization method based on self-organizing maps.
IEEE Trans. Neural Networks
Chip-Hong Chang, Pengfei Xu, Rui Xiao, Thambipillai Srikanthan
2005 J jnl
Self-organizing topological tree for online vector quantization and data clustering.
IEEE Trans. Syst. Man Cybern. Part B
Pengfei Xu, Chip-Hong Chang, Andrew P. Paplinski
2005 — conf
VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers.
Asia-Pacific Computer Systems Architecture Conference
Ravi Kumar Satzoda, Chip-Hong Chang
2005 — conf
Wavelet transform to hybrid support vector machine and hidden Markov model for speech recognition.
ISCAS (4)
Yu Shao, Chip-Hong Chang
2004 — conf
A New Method for Eye Extraction from Facial Image.
DELTA
Xiaoyun Deng, Chip-Hong Chang, Erwin Brandle
2004 — conf
A new contention resolution algorithm for the design of minimal logic depth multiplierless filters.
ISCAS (3)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
2004 — conf
Design of residue-to-binary converter for a new 5-moduli superset residue number system.
ISCAS (2)
Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang
2004 — conf
Efficient algorithms for common subexpression elimination in digital filter design.
ICASSP (5)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
2004 — conf
Frequency sensitive self-organizing maps and its application in color quantization.
ISCAS (5)
Chip-Hong Chang, Pengfei Xu
2004 — conf
HWP: a new insight into canonical signed digit.
ISCAS (5)
Fei Xu, Chip-Hong Chang, Ching-Chuen Jong
2004 — conf
Local Search Method for FIR Filter Coefficients Synthesis.
DELTA
Zhi Ye, Chip-Hong Chang
2004 — conf
Performance Evaluation of Direct Form FIR Filter with Merged Arithmetic Architecture.
DELTA
Zhi Ye, Ravi Kumar Satzoda, Udit Sharma, Naveen Nazimudeen, Chip-Hong Chang
2004 — conf
Self-organizing topological tree.
ISCAS (5)
Pengfei Xu, Chip-Hong Chang
2004 J jnl
Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang
2003 — conf
A novel hybrid pass logic with static CMOS output drive full-adder cell.
ISCAS (5)
Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang
2003 — conf
An adaptive initialization technique for color quantization by self organizing feature map.
ICASSP (3)
Chip-Hong Chang, Rui Xiao, Thambipillai Srikanthan
2003 — conf
Design of a high speed reverse converter for a new 4-moduli set residue number system.
ISCAS (4)
Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang
2003 — conf
FPGA implementation of a frequency adaptive learning SOFM for digital color still imaging.
ISCAS (2)
Shibu Menon, Chip-Hong Chang, Rui Xiao
2003 — conf
Low voltage, low power (5: 2) compressor cell for fast arithmetic circuits.
ICASSP (2)
Jiangmin Gu, Chip-Hong Chang
2003 — conf
New efficient residue-to-binary converters for 4-moduli set {2
ISCAS (4)
Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan
2003 — conf
Ultra low voltage, low power 4-2 compressor for high speed multiplications.
ISCAS (5)
Jiangmin Gu, Chip-Hong Chang
2002 — conf
A MSB-biased self-organizing feature map for still color image compression.
APCCAS (2)
Chip-Hong Chang, Rui Xiao, Thambipillai Srikanthan
2002 — conf
An efficient architecture for adaptive progressive thresholding.
APCCAS (1)
Hui Tian, Siew Kei Lam, Thambipillai Srikanthan, Chip-Hong Chang
2002 — conf
An interconnect optimized floorplanning of a scalar product macrocell.
ISCAS (1)
Jiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo
2002 J jnl
Boolean Matching Filters Based on Row and Column Weights of Reed-Muller Polarity Coefficient Matrix.
VLSI Design
Chip-Hong Chang, Bogdan J. Falkowski
2002 J jnl
Field programable gate array based architecture for real time image segmentation by region growing algorithm.
J. Electronic Imaging
Chip-Hong Chang, Hui Tian, Thambipillai Srikanthan, Chai-Soon Lim
2002 — conf
Fuzzy-ART based digital watermarking scheme.
APCCAS (1)
Chip-Hong Chang, Zhi Ye, Mingyan Zhang
2002 — conf
On the Initialization and Training Methods for Kohonen Self-Organizing Feature Maps in Color Image Quantization.
DELTA
Rui Xiao, Chip-Hong Chang, Thambipillai Srikanthan
2000 J jnl
Minimization of
VLSI Design
Bogdan J. Falkowski, Chip-Hong Chang
1999 J jnl
An Efficient Algorithm for the Calculation of Generalized Adding and Arithmetic Transforms From Disjoint Cubes of Boolean Functions.
VLSI Design
Bogdan J. Falkowski, Chip-Hong Chang
1999 — conf
Optimization of partially-mixed-polarity Reed-Muller expansions.
ISCAS (1)
Bogdan J. Falkowski, Chip-Hong Chang
1999 — conf
Reed-Muller weight and literal vectors for NPN classification.
ISCAS (1)
Chip-Hong Chang, Bogdan J. Falkowski
1998 J jnl
Spherical Harmonic Modeling of a 0.05 μm Base BJT: A Comparison with Monte Carlo and Asymptotic Analysis.
VLSI Design
Chip-Hong Chang, C.-K. Lin, Neil Goldsman, Isaak D. Mayergoyz
1997 J jnl
Forward and Inverse Transformations Between Haar Spectra and Ordered Binary Decision Diagrams of Boolean Functions.
IEEE Trans. Computers
Bogdan J. Falkowski, Chip-Hong Chang
1995 — conf
Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functions.
ASP-DAC
Chip-Hong Chang, Bogdan J. Falkowski
1995 C conf
Generation of Multi-Polarity Arithmetic Transform from Reduced Representation of Boolean Functions.
ISCAS
Bogdan J. Falkowski, Chip-Hong Chang
1994 C conf
Efficient Algorithms for the Calculation of Arithmetic Spectrum from OBDD & Synthesis of OBDD from Arithmetic Spectrum for Incompletely Specified Boolean Functions.
ISCAS
Bogdan J. Falkowski, Chip-Hong Chang
1993 J jnl
Design and Performance of a New Multi-Lane AVI System.
J. Intell. Transp. Syst.
M. A. Do, Chip-Hong Chang