Chiou-Yng Lee

100 papers A 2B 1C 9Journal 59Unranked 29
YearRankTypeTitle / Venue / Authors
2022 J jnl
Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor.
IEEE Access
Chiou-Yng Lee, Medien Zeghid, Anissa Sghaier, Hassan Yousif Ahmed, Jiafeng Xie
2022 C conf
Hardware Implementation of High-Performance Polynomial Multiplication for KEM Saber.
ISCAS
Yazheng Tu, Pengzhou He, Chiou-Yng Lee, Danai Chasaki, Jiafeng Xie
2021 C conf
CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy.
ICCD
Jiafeng Xie, Pengzhou He, Chiou-Yng Lee
2020 — conf
Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2
ASP-DAC
Chiou-Yng Lee, Jiafeng Xie
2019 J jnl
Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Jiafeng Xie
2019 C conf
Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy.
ICCD
Chiou-Yng Lee, Jiafeng Xie
2019 A conf
Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity.
FPGA
Jiafeng Xie, Chiou-Yng Lee
2019 — conf
High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2
HOST
Chiou-Yng Lee, Jiafeng Xie
2019 — conf
LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field.
ACM Great Lakes Symposium on VLSI
Jiafeng Xie, Chiou-Yng Lee
2019 C conf
Low-Complexity Systolic Multiplier for GF(2
ISCAS
Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher
2019 J jnl
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis.
IEEE Trans. Very Large Scale Integr. Syst.
Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher, Zhi-Hong Mao
2019 J jnl
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach.
IEEE Trans. Very Large Scale Integr. Syst.
Jeng-Shyang Pan, Chiou-Yng Lee, Anissa Sghaier, Zeghid Medien, Jiafeng Xie
2018 J jnl
Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field.
IEEE Access
Chiou-Yng Lee, Chia-Chen Fan, Jiafeng Xie, Shyan-Ming Yuan
2018 J jnl
High-throughput Dickson basis multiplier with a trinomial for lightweight cryptosystems.
IET Comput. Digit. Tech.
Che Wun Chiou, Cheng-Min Lee, Yuh-Sien Sun, Chiou-Yng Lee, Jim-Min Lin
2018 C conf
Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm.
ICCD
Chiou-Yng Lee, Jiafeng Xie
2018 J jnl
Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Qiliang Shao, Zhenji Hu, Shaik Nazeem Basha, Zhiping Zhang, Zhiqiang Wu, Chiou-Yng Lee, Jiafeng Xie
2018 J jnl
Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2
IEEE Trans. Multi Scale Comput. Syst.
Jiafeng Xie, Pramod Kumar Meher, Xiaojun Zhou, Chiou-Yng Lee
2017 — conf
An efficient FPGA-based accelerator design for convolution.
iCAST
Pengfei Song, Jeng-Shyang Pan, Chun-Sheng Yang, Chiou-Yng Lee
2017 J jnl
Gaussian normal basis multiplier over GF(2
IET Circuits Devices Syst.
Che Wun Chiou, Yuh-Sien Sun, Cheng-Min Lee, Jim-Min Lin, Tai-Pao Chuang, Chiou-Yng Lee
2017 — conf
Hardware implementation of double basis multiplier using TMVP approach over GF (2
iCAST
Shu-Xia Dong, Jeng-Shyang Pan, Chun-Sheng Yang, Chiou-Yng Lee
2017 J jnl
Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition.
IEEE Trans. Very Large Scale Integr. Syst.
Chiou-Yng Lee, Pramod Kumar Meher, Chia-Chen Fan, Shyan-Ming Yuan
2017 J jnl
Low-latency digit-serial dual basis multiplier for lightweight cryptosystems.
IET Inf. Secur.
Che Wun Chiou, Chiou-Yng Lee, Jim-Min Lin, Yun-Chi Yeh, Jeng-Shyang Pan
2016 J jnl
Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach.
IEEE Trans. Very Large Scale Integr. Syst.
Chiou-Yng Lee, Pramod Kumar Meher, Chung-Hsin Liu
2016 J jnl
Comment on "Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Pramod Kumar Meher
2015 J jnl
A smart safety cane for human fall detection.
Int. J. Ad Hoc Ubiquitous Comput.
Ping-Hsu Chen, Yung-Hui Li, Che Wun Chiou, Chiou-Yng Lee, Jim-Min Lin
2015 J jnl
Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Pramod Kumar Meher
2015 J jnl
Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chung-Hsin Liu, Chiou-Yng Lee, Pramod Kumar Meher
2015 — conf
Efficient Digit-Serial Multiplier Employing Karatsuba Algorithm.
ICGEC (2)
Shyan-Ming Yuan, Chiou-Yng Lee, Chia-Chen Fan
2015 J jnl
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Pramod Kumar Meher
2015 C conf
Efficient subquadratic parallel multiplier based on modified SPB of GF(2
ISCAS
Jeng-Shyang Pan, Pramod Kumar Meher, Chiou-Yng Lee, Hong-Hai Bai
2015 — conf
Implementation of an FPGA-Based Vision Localization.
ICGEC (2)
Wen-Yo Lee, Bo-Jhih Chen, Chieh-Tsai Wu, Ching-Long Shih, Ya-Hui Tsai, Yi-Chih Fan, Chiou-Yng Lee, Ti-Hung Chen
2015 — conf
Problems on Gaussian Normal Basis Multiplication for Elliptic Curve Cryptosystem.
ICGEC (2)
Che Wun Chiou, Yuh-Sien Sun, Cheng-Min Lee, Y.-L. Chiu, Jim-Min Lin, Chiou-Yng Lee
2015 J jnl
Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Pramod Kumar Meher
2015 — conf
Subquadratic Space-Complexity Parallel Systolic Multiplier Based on Karatsuba Algorithm and Block Recombination.
ICGEC (2)
Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin
2015 J jnl
Subquadratic space complexity Gaussian normal basis multipliers over GF(2
IET Circuits Devices Syst.
Jeng-Shyang Pan, Chiou-Yng Lee, Yao Li
2015 — conf
Supporting Physical Agents in an Interactive e-book.
ICGEC (2)
Jim-Min Lin, Che Wun Chiou, Chiou-Yng Lee, Jing-Rui Hsiao
2015 J jnl
Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Reza Azarderakhsh, Mehran Mozaffari Kermani, Siavash Bayat Sarmadi, Chiou-Yng Lee
2014 J jnl
A Linear Time Pessimistic Diagnosis Algorithm for Hypermesh Multiprocessor Systems under the PMC Model.
IEEE Trans. Computers
Hong-Chun Hsu, Kuang-Shyr Wu, Cheng-Kuan Lin, Chiou-Yng Lee, Chien-Ping Chang
2014 J jnl
Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures.
IEEE Trans. Circuits Syst. II Express Briefs
Siavash Bayat Sarmadi, Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee
2014 J jnl
Efficient $M$ -ary Exponentiation over $GF(2^{m})$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Pramod Kumar Meher, Chien-Ping Chang
2014 J jnl
Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Chun-Sheng Yang, Bimal Kumar Meher, Pramod Kumar Meher, Jeng-Shyang Pan
2014 J jnl
Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach.
IEEE Trans. Computers
Jeng-Shyang Pan, Reza Azarderakhsh, Mehran Mozaffari Kermani, Chiou-Yng Lee, Wen-Yo Lee, Che Wun Chiou, Jim-Min Lin
2014 J jnl
Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over GF(2
IEEE Trans. Very Large Scale Integr. Syst.
Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee, Siavash Bayat Sarmadi
2014 — conf
Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm.
ISIC
Chiou-Yng Lee, Pramod Kumar Meher, Wen-Yo Lee
2013 — conf
Digit-Serial GNB Multiplier Based on TMVP Approach over GF(2m).
RVSP
Chun-Sheng Yang, Jeng-Shyang Pan, Chiou-Yng Lee
2013 — conf
Hybrid Digit-Serial Multiplier for Shifted Polynomial Basis of GF(2 m ).
ICGEC
Chiou-Yng Lee, Wen-Yo Lee, Che Wun Chiou, Jeng-Shyang Pan, Cheng-Huai Ni
2013 J jnl
Low space-complexity digit-serial dual basis systolic multiplier over Galois field GF(2
IET Inf. Secur.
Ying Yan Hua, Jim-Min Lin, Che Wun Chiou, Chiou-Yng Lee, Yong Huan Liu
2013 J jnl
Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jeng-Shyang Pan, Chiou-Yng Lee, Pramod Kumar Meher
2013 — conf
Pipeline Design of Bit-Parallel Gaussian Normal Basis Multiplier over GF(2m).
ICGEC
Che Wun Chiou, Jim-Min Lin, Yu-Ku Li, Chiou-Yng Lee, Tai-Pao Chuang, Yun-Chi Yeh
2012 — conf
A Scalable Architecture for Dual Basis GF(2m) Multiplications.
ISBAST
Liang-Hwa Chen, Po-Lun Chang, Yen-Ching Chang, Chiou-Yng Lee
2012 J jnl
Fault-tolerant Gaussian normal basis multiplier over GF(2
IET Inf. Secur.
Tai-Pao Chuang, Che Wun Chiou, Shun-Shii Lin, Chiou-Yng Lee
2012 J jnl
Low-complexity Gaussian normal basis multiplier over GF(2
IET Inf. Secur.
Che Wun Chiou, Hung Wei Chang, Wen-Yew Liang, Chiou-Yng Lee, Jim-Min Lin, Yun-Chi Yeh
2012 J jnl
Palindromic-like representation for Gaussian normal basis multiplier over GF(2
IET Inf. Secur.
Che Wun Chiou, Tai-Pao Chuang, Shun-Shii Lin, Chiou-Yng Lee, Jim-Min Lin, Yun-Chi Yeh
2012 J jnl
Scalable Gaussian Normal Basis Multipliers over GF(2 m ) Using Hankel Matrix-Vector Representation.
J. Signal Process. Syst.
Chiou-Yng Lee, Che Wun Chiou
2012 — conf
Super Digit-Serial Systolic Multiplier over GF(2^m).
ICGEC
Chiou-Yng Lee
2011 J jnl
Combined circuit architecture for computing normal basis and Montgomery multiplications over GF(2
Int. J. Auton. Adapt. Commun. Syst.
Chiou-Yng Lee, Chia-Chen Fan, Erl-Huei Lu
2011 J jnl
Multiplexer implementation of low-complexity polynomial basis multiplier in GF(m
Inf. Process. Lett.
Che Wun Chiou, Chiou-Yng Lee, Yun-Chi Yeh
2011 — conf
Novel Mastrovito Multiplier over GF(2m) Using Trinomial.
ICGEC
Che Wun Chiou, Jim-Min Lin, Chiou-Yng Lee, Chi-Ting Ma
2011 — conf
Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula.
ICGEC
Chiou-Yng Lee, Pramod Kumar Meher
2010 J jnl
Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2
IEEE Trans. Very Large Scale Integr. Syst.
Chiou-Yng Lee, Pramod Kumar Meher, Jagdish Chandra Patra
2010 J jnl
Concurrent Error Detection in Multiplexer-Based Multipliers for Normal Basis of GF(2
J. Signal Process. Syst.
Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin
2010 — conf
Concurrent Error Detection in Shifted Dual Basis Multiplier over GF(2m) Using Cyclic Code Approach.
AINA Workshops
Chiou-Yng Lee, Yu-Hsin Chiu, Jung-Hui Chiu
2010 — conf
Concurrent Error Detection in Systolic Array AB^2 Multiplier Using Linear Codes.
CASoN
Chiou-Yng Lee
2010 J jnl
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2
Integr.
Chiou-Yng Lee
2010 J jnl
Concurrent error detection in semi-systolic dual basis multiplier over GF(2
IET Circuits Devices Syst.
Che Wun Chiou, Wen-Yew Liang, Hung Wei Chang, Jim-Min Lin, Chiou-Yng Lee
2010 J jnl
Efficient bit-parallel multipliers over finite fields GF(2
Comput. Electr. Eng.
Chiou-Yng Lee, Pramod Kumar Meher
2010 C conf
Error-Correcting Codes for Concurrent Error Correction in Bit-Parallel Systolic and Scalable Multipliers for Shifted Dual Basis of GF(2
ISPA
Chiou-Yng Lee
2010 — conf
Fast Optimal Normal Basis Multiplier with Type-2kw Over GF (2m).
CASoN
Che Wun Chiou, Jim-Min Lin, Chiou-Yng Lee
2009 — conf
An optimized design for serial-parallel finite field multiplication over
ASP-DAC
Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee
2009 J jnl
Concurrent Error Detection and Correction in Gaussian Normal Basis Multiplier over GF(2^m).
IEEE Trans. Computers
Che Wun Chiou, Chin-Chen Chang, Chiou-Yng Lee, Ting-Wei Hou, Jim-Min Lin
2009 J jnl
Concurrent error detection and correction in dual basis multiplier over GF(2
IET Circuits Devices Syst.
Che Wun Chiou, Chiou-Yng Lee, Jim-Min Lin, Ting-Wei Hou, Chin-Chen Chang
2009 — conf
Implementation of an interactive mobile robot over mixed reality.
ROBIO
Wen-Yo Lee, Jhu-Syuan Guo, Chiou-Yng Lee, Chan-An Pao, Ta-Chih Hung
2009 C conf
Scalable Serial-parallel Multiplier over GF(2
ISCAS
Pramod Kumar Meher, Chiou-Yng Lee
2009 J jnl
Unified dual-field multiplier in GF(P) and GF(2
IET Inf. Secur.
Che Wun Chiou, Chiou-Yng Lee, Jim-Min Lin
2008 — conf
Combined circuit architecture for computing normal basis and montgomery multiplications over GF(2
Mobility Conference
Chin-Chin Chen, Chiou-Yng Lee, Erl-Huei Lu
2008 — conf
Concurrent Error Detection in Digit-Serial Normal Basis Multiplication over GF(2m).
AINA Workshops
Chiou-Yng Lee
2008 C conf
Efficient Bit-Parallel Multipliers in Composite Fields.
APSCC
Chiou-Yng Lee, Pramod Kumar Meher
2008 J jnl
Low-Complexity Parallel Systolic Montgomery Multipliers over GF(2
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chiou-Yng Lee
2008 J jnl
Low-complexity bit-parallel systolic multipliers over GF(2
Integr.
Chiou-Yng Lee
2008 J jnl
Multiplexer-based bit-parallel systolic multipliers over GF(2
Comput. Electr. Eng.
Chiou-Yng Lee
2008 J jnl
New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2
J. Signal Process. Syst.
Chiou-Yng Lee, Che Wun Chiou
2008 J jnl
Scalable and Systolic Montgomery Multipliers over GF(2
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chin-Chin Chen, Chiou-Yng Lee, Erl-Huei Lu
2007 — conf
Low-Complexity Parallel Systolic Architectures for Computing Multiplication and Squaring over FG(2
AINA Workshops (1)
Chiou-Yng Lee, Yung-Hui Chen
2007 J jnl
Scalable and systolic Montgomery multiplier over GF(2
IET Circuits Devices Syst.
Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin, Chin-Chen Chang
2007 J jnl
Unified Parallel Systolic Multiplier Over
J. Comput. Sci. Technol.
Chiou-Yng Lee, Yung-Hui Chen, Che Wun Chiou, Jim-Min Lin
2006 J jnl
Concurrent Error Detection in Montgomery Multiplication over
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Che Wun Chiou, Chiou-Yng Lee, An-Wen Deng, Jim-Min Lin
2006 J jnl
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2
J. Electron. Test.
Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin
2006 J jnl
Low-Complexity Bit-Parallel Multiplier over GF(2
J. Comput. Sci. Technol.
Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou
2006 B conf
Low-Complexity Bit-Parallel Systolic Multipliers over GF(2m).
SMC
Chiou-Yng Lee, Chin-Chin Chen, Yuan-Ho Chen, Erl-Huei Lu
2006 — conf
New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm.
APCCAS
Chiou-Yng Lee, Yu-Hsin Chiu, Che Wun Chiou
2005 J jnl
Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2
J. Electron. Test.
Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin
2005 J jnl
Efficient Design of Low-Complexity Bit-Parallel Systolic Hankel Multipliers to Implement Multiplication in Normal and Dual Bases of GF (2
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chiou-Yng Lee, Che Wun Chiou
2005 J jnl
Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2
IEEE Trans. Computers
Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu
2005 J jnl
Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm.
Comput. Electr. Eng.
Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin
2005 J jnl
Multiplexer-based double-exponentiation for normal basis of GF(2
Comput. Secur.
Che Wun Chiou, Chiou-Yng Lee
2004 A conf
Low-complexity linear array multiplier for normal basis of type-II.
ICME
Chiou-Yng Lee, Chung-Jyi Chang
2003 J jnl
Low-Latency Bit-Parallel Systolic Multiplier for Irreducible x
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chiou-Yng Lee
2002 — conf
Low-complexity systolic multiplier over GF(2
APCCAS (1)
Chiou-Yng Lee, Ya-Cheng Lu, Erl-Huei Lu
2001 J jnl
Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials.
IEEE Trans. Computers
Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee
2001 — conf
New bit-parallel systolic multipliers for a class of GF(2m).
ISCAS (4)
Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee