Chingwei Yeh

42 papers A* 1C 1Journal 19Unranked 21
YearRankTypeTitle / Venue / Authors
2024 — conf
Performance Evaluation of MEMS Vibration Sensors for Throat Microphones.
IEEE SENSORS
Che-Yu Hsu, Po-Han Chen, Ting-Yi Chen, Shang-Yu Lin, Ching-Jen Wang, Chingwei Yeh, Tay-Jyi Lin, Pei-Zen Chang, Wei-Chang Li
2023 J jnl
A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN.
IEEE Trans. Circuits Syst. II Express Briefs
Tay-Jyi Lin, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang
2023 — conf
Force-Sensing Intelligent Vise for Cutting Dynamics Monitoring in Machining.
SENSORS
Po-Han Chen, Tay-Jyi Lin, Chingwei Yeh, Pei-Zen Chang, Wei-Chang Li
2022 — conf
A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients.
ASP-DAC
Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang
2017 — conf
Approximate Distributed Arithmetic for Variable-Latency Table Lookup.
NGCAS
Yi-Hsuan Ting, Tay-Jyi Lin, Cheng-Chun Chang, Chih-Chien Hu, Chingwei Yeh, Jinn-Shyan Wang
2016 — conf
A low complexity edge-preserved image compression algorithm for LCD overdrive.
GCCE
Chao-Yang Chang, Chung-Hsun Huang, Hui-Fu Chen, Chingwei Yeh, Yuan-Sun Chu, Tay-Jyi Lin
2016 — conf
Variable-length VLIW encoding for code size reduction in embedded processors.
SoCC
Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen
2014 — conf
Maintaining color fidelity for dual-shot HDR imaging.
ICCE-TW
Chingwei Yeh, Chen-Yao Tsai, Tay-Jyi Lin, Jiun-In Guo
2013 J jnl
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections.
IEEE Trans. Very Large Scale Integr. Syst.
Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang
2013 — conf
Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS.
ISSCC
Jian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang
2012 J jnl
Towards Process Variation-Aware Power Gating.
IEEE Trans. Very Large Scale Integr. Syst.
Chingwei Yeh, Yuan-Chang Chen, Jinn-Shyan Wang
2011 J jnl
Design of High-Performance CMOS Level Converters Considering PVT Variations.
IEICE Trans. Electron.
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh
2011 — conf
Low power shift registers for megabits CMOS image sensors.
ASICON
Jinn-Shyan Wang, Tsung-Han Hsieh, Keng-Jui Chang, Chingwei Yeh
2011 J jnl
Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy.
ACM Trans. Archit. Code Optim.
Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh
2011 — conf
RSCE-aware ultra-low-voltage 40-nm CMOS circuits.
ISOCC
Jinn-Shyan Wang, Keng-Jui Chang, Shu-Yi Yang, Tsung-Han Hsieh, Chingwei Yeh
2011 — conf
Variation-resilient voltage generation for SRAM weak cell testing.
ASICON
Chingwei Yeh, Yan-Nan Liu, Jinn-Shyan Wang, Pei-Yao Chang
2010 J jnl
Adaptive Pipeline voltage Scaling in High Performance Microprocessor.
J. Circuits Syst. Comput.
Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh
2010 J jnl
Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays.
IEICE Trans. Electron.
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh
2008 J jnl
High-Speed and Low-Power Design Techniques for TCAM Macros.
IEEE J. Solid State Circuits
Chao-Ching Wang, Jinn-Shyan Wang, Chingwei Yeh
2007 — conf
A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS.
ISSCC
Jinn-Shyan Wang, Jian-Shiun Chen, Yi-Ming Wang, Chingwei Yeh
2007 — conf
Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling.
HiPEAC
Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh
2006 — conf
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications.
DATE Designers' Forum
Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang
2006 — conf
An 830mW, 586kbps 1024-bit RSA chip design.
DATE Designers' Forum
Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang
2006 J jnl
An AND-type match-line scheme for high-performance energy-efficient content addressable memories.
IEEE J. Solid State Circuits
Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh
2006 C conf
Design of STR level converters for SoCs using the multi-island dual-VDD design technique.
ISCAS
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu
2006 J jnl
Performance-driven technology mapping with MSG partition and selective gate duplication.
ACM Trans. Design Autom. Electr. Syst.
Chi-Shong Wang, Chingwei Yeh
2006 J jnl
Power minimization for dynamic PLAs.
IEEE Trans. Very Large Scale Integr. Syst.
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh
2006 — conf
TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines.
ISSCC
Jinn-Shyan Wang, Chao-Ching Wang, Chingwei Yeh
2006 A* conf
Timing driven power gating.
DAC
De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh
2005 — conf
A low-power high-SFDR CMOS direct digital frequency synthesizer.
ISCAS (2)
Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh
2005 J jnl
Design techniques for single-low-V
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Hung-Yu Li, Chingwei Yeh, Tien-Fu Chen
2005 — conf
Power minimization for dynamic PLAs.
ASP-DAC
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh
2004 J jnl
The CMOS carry-forward adders.
IEEE J. Solid State Circuits
Chung-Hsun Huang, Jinn-Shyan Wang, Chingwei Yeh, Chih-Jen Fang
2001 J jnl
An adaptive path selection method for delay testing.
IEEE Trans. Instrum. Meas.
Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das
2001 J jnl
Analysis and design of high-speed and low-power CMOS PLAs.
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Ching-Rong Chang, Chingwei Yeh
2001 J jnl
Cell-based layout techniques supporting gate-level voltage scaling for low power.
IEEE Trans. Very Large Scale Integr. Syst.
Chingwei Yeh, Yin-Shuin Kang
2000 J jnl
Cell-based layout techniques supporting gate-level voltage scaling for low power.
IEEE Trans. Very Large Scale Integr. Syst.
Chingwei Yeh, Yin-Shuin Kang
1999 — conf
A cell selection strategy for low power applications.
ISCAS (6)
Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang
1999 — conf
A simulated annealing based method supporting dual supply voltages in standard cell placement.
ISCAS (1)
Chingwei Yeh, Yin-Shuin Kang
1999 — conf
Power reduction through iterative gate sizing and voltage scaling.
ISCAS (1)
Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
1996 J jnl
On the integration of partitioning and global routing for rectilinear placement problems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chingwei Yeh, Chi-Shong Wang
1994 J jnl
Block-oriented programmable design with switching network interconnect.
IEEE Trans. Very Large Scale Integr. Syst.
Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel