Ching-Yuan Yang

57 papers A 2C 5Journal 20Unranked 30

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A 2.9-Gb/s Spread-Spectrum Clocking Transceiver Using Phase Interpolation for Chip-to-Chip Links. NewCAS Shu-Chi Wang, Wan-Yu Yu, Ching-Yuan Yang
2023	—	`conf`	A 30-GHz Frequency Doubler Using a Current Folding Technique in 90-nm CMOS Technology. MOCAST Ke-Chiao Chou, Chun-Hung Lin, Ching-Yuan Yang
2023	—	`conf`	Behavior Simulation of CDR for SSC System With a Compact Quarter-Rate Linear Phase Detector. ISOCC Shu-Chi Wang, Ching-Yuan Yang
2023	—	`conf`	Behavior Simulation of SSC Generator With Adjustable Modulation Frequency and Depth. ISOCC Wan-Yu You, Ching-Yuan Yang
2022	—	`conf`	A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion. VLSI-DAT Shao-Yu Shu, Chun-Hung Lin, Ching-Yuan Yang
2022	—	`conf`	A 80-MHz 91.2 ppm/°C Self-Biased Frequency-Locked-Loop Timer. ISOCC Tsung-Ying Chen, Ching-Yuan Yang, Dung-An Wang
2021	—	`conf`	A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth. A-SSCC Yen-Kuei Lu, Miao-Shan Li, Ching-Yuan Yang, Chin-Lung Lin
2021	—	`conf`	A Self Synchronized-Switch Rectifier for Piezoelectric-Vibration Energy-Harvesting Systems. ISOCC Yong-Zheng Wang, Ching-Yuan Yang
2021	J	`jnl`	A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links. IEEE Trans. Very Large Scale Integr. Syst. Ching-Yuan Yang, Miao-Shan Li, Ai-Jia Chuang
2020	—	`conf`	A Flipping Active-Diode Rectifier for Piezoelectric-Vibration Energy-Harvesting. ECCTD Wan-Ling Wu, Ching-Yuan Yang, Dung-An Wang
2020	—	`conf`	A High-Efficiency Parallel-SSHI Rectifier for Piezoelectric Energy Harvesting. ISOCC Hao-Hsiang Hsu, Ching-Yuan Yang, Dung-An Wang
2019	—	`conf`	A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection. SoCC Guan-Min Luo, Ching-Yuan Yang
2019	—	`conf`	A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL. SoCC You-Sheng Lin, Miao-Shan Li, Ching-Yuan Yang
2019	—	`conf`	A Spur-Suppression Technique for Frequency Synthesizer with Pulse-Width to Current Conversion. ISPACS Po-Yu Hsieh, Shao-Yu Shu, Ching-Yuan Yang
2019	—	`conf`	Cascading Convolutional Neural Network for Steel Surface Defect Detection. AHFE (14) Chih-Yang Lin, Cheng-Hsun Chen, Ching-Yuan Yang, Fityanul Akhyar, Chao-Yung Hsu, Hui-Fuang Ng
2019	—	`conf`	Flipping Rectifiers for Piezoelectric Vibration Energy Harvesting. ISOCC Wan-Ling Wu, Yong-Zheng Wang, Ching-Yuan Yang
2019	—	`conf`	PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems. ISOCC Miao-Shan Li, Yen-Kuei Lu, Ching-Yuan Yang, Chin-Lung Lin
2017	—	`conf`	A 1.5-Gb/s adaptive equalizer with periodically embedded clock encoding for intra-panel interfaces. ISOCC Chia-Chi Liu, Ching-Yuan Yang
2017	—	`conf`	A 1.5-Gb/s equalizer with adaptive swing controller for TFT-LCD driver. ISOCC Yen-Chen Lin, Ching-Yuan Yang, James Chang
2017	—	`conf`	Realization of buck converter with adaptive variable-frequency control. SoCC Ching-Yuan Yang, Jen-Yan Huang, Jun-Hong Weng
2017	—	`conf`	W2A: Analog-to-digital converters and low-noise amplifiers. SoCC Ching-Yuan Yang
2016	—	`conf`	A 90-nm CMOS Frequency Synthesizer with a Tripler for 60-GHz Wireless Communication Systems. ISVLSI Po-Tsang Chen, Ching-Yuan Yang
2016	J	`jnl`	A Reference Voltage Interpolation-Based Calibration Method for Flash ADCs. IEEE Trans. Very Large Scale Integr. Syst. Hsuan-Yu Chang, Ching-Yuan Yang
2015	J	`jnl`	A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling. IEEE Trans. Very Large Scale Integr. Syst. Jung-Mao Lin, Ching-Yuan Yang, Hsin-Ming Wu
2015	J	`jnl`	A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment. IEEE Trans. Circuits Syst. I Regul. Pap. Jung-Mao Lin, Ching-Yuan Yang
2014	C	`conf`	A high-speed low-power calibrated flash ADC. ISCAS Hsuan-Yu Chang, Ching-Yuan Yang
2013	—	`conf`	A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS. ESSCIRC Chih-Hsiang Chang, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng, Nai-Chen Cheng
2012	—	`conf`	A 22-GHz low-power frequency synthesizer in 0.18-um CMOS. ISCIT Ching-Yuan Yang, Jia-Jiun Lin, Chih-Hsiang Chang
2012	C	`conf`	A chip-to-chip clock-deskewing circuit for 3-D ICs. ISCAS Ai-Jia Chuang, Yu Lee, Ching-Yuan Yang
2011	J	`jnl`	A 0.5/0.8-V 9-GHz Frequency Synthesizer With Doubling Generation in 0.13-μm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Ching-Yuan Yang, Chih-Hsiang Chang, Jun-Hong Weng, Hsin-Ming Wu
2011	J	`jnl`	A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35- μ m SiGe BiCMOS. IEEE J. Solid State Circuits Ching-Yuan Yang, Jun-Hong Weng, Hsuan-Yu Chang
2011	A	`conf`	A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique. ISLPED Jun-Hong Weng, Ching-Yuan Yang, Yi-Lin Jhu
2010	A	`conf`	An embedded wide-range and high-resolution CLOCK jitter measurement circuit. DATE Yu Lee, Ching-Yuan Yang, Nai-Chen Daniel Cheng, Ji-Jan Chen
2009	J	`jnl`	A Delta-Sigma PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology. IEEE Trans. Circuits Syst. I Regul. Pap. Ching-Yuan Yang, Chih-Hsiang Chang, Wen-Ger Wong
2008	—	`conf`	A 2.5Gb/s oversampling clock and data recovery circuit with frequency calibration technique. APCCAS Kai Pong Wu, Ching-Yuan Yang, Jung-Mao Lin
2008	J	`jnl`	A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ching-Yuan Yang, Chih-Hsiang Chang, Wen-Ger Wong
2008	J	`jnl`	A PWM and PAM Signaling Hybrid Technology for Serial-Link Transceivers. IEEE Trans. Instrum. Meas. Ching-Yuan Yang, Yu Lee
2008	—	`conf`	A programmable duty cycle corrector based on delta-sigma modulated PWM mechanism. APCCAS Gung-Yu Lin, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng
2008	J	`jnl`	Acoustic-Resonance-Free High-Frequency Electronic Ballast for Metal Halide Lamps. IEEE Trans. Ind. Electron. Chin-Sien Moo, Chun-Kai Huang, Ching-Yuan Yang
2008	J	`jnl`	Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ching-Yuan Yang, Ken-Hao Chang
2007	J	`jnl`	A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation. IEICE Trans. Electron. Ching-Yuan Yang, Jung-Mao Lin
2007	—	`conf`	A Fast-Locking Agile Frequency Synthesizer for MIMO Dual-mode WiFi / WiMAX Applications. ICECS Meng-Ting Tsai, Ching-Yuan Yang
2006	C	`conf`	A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique. ISCAS Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, Ching-Yuan Yang
2006	—	`conf`	A 3.125-GHz Limiting Amplifier for Optical Receiver System. APCCAS Hsin-Ming Wu, Ching-Yuan Yang
2006	—	`conf`	A 6.5-GHz LC VCO with Integrated-Transformer Tuning. APCCAS Chia-Chieh Tu, Ching-Yuan Yang
2006	J	`jnl`	A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector. IEICE Trans. Electron. Ching-Yuan Yang, Yu Lee, Cheng-Hsing Lee
2006	C	`conf`	A frequency synthesizer realized by a transformer-based voltage-controlled oscillator for IEEE 802.11a/b/g channels. ISCAS Meng-Ting Tsai, Ching-Yuan Yang
2006	C	`conf`	A low-noise microsensor amplifier with automatic gain control system. ISCAS Jun-Hong Weng, Chong-Jng Yu, Ching-Yuan Yang, Peng-Chang Yang
2006	J	`jnl`	High-Frequency Low-Noise Voltage-Controlled IEICE Trans. Electron. Ching-Yuan Yang, Meng-Ting Tsai
2005	—	`conf`	A 0.18-µm CMOS 1-Gb/s serial link transceiver by using PWM and PAM techniques. ISCAS (2) Ching-Yuan Yang, Yu Lee
2005	—	`conf`	A high-frequency phase-compensation fractional-N frequency synthesizer. ISCAS (5) Ching-Yuan Yang, Jen-Wen Chen, Meng-Ting Tsai
2002	J	`jnl`	A wide-range delay-locked loop with a fixed latency of one clock cycle. IEEE J. Solid State Circuits Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu
2001	J	`jnl`	A one-wire approach for skew-compensating clock distribution based on bidirectional techniques. IEEE J. Solid State Circuits Ching-Yuan Yang, Shen-Iuan Liu
2000	J	`jnl`	A 900-MHz 1-V CMOS frequency synthesizer. IEEE J. Solid State Circuits Guang-Kaai Dehng, Ching-Yuan Yang, June-Ming Hsu, Shen-Iuan Liu
2000	J	`jnl`	Clock-deskew buffer using a SAR-controlled delay-locked loop. IEEE J. Solid State Circuits Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang, Shen-Iuan Liu
2000	J	`jnl`	Fast-switching frequency synthesizer with a discriminator-aided phase detector. IEEE J. Solid State Circuits Ching-Yuan Yang, Shen-Iuan Liu
1998	J	`jnl`	New dynamic flip-flops for high-speed dual-modulus prescaler. IEEE J. Solid State Circuits Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu, Shen-Iuan Liu