Ching-Yu Chin

13 papers A* 1A 4Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2017 — conf
An analytical placer for heterogeneous FPGAs via rough-placed packing.
VLSI-DAT
Wan-Ning Wu, Chen Chen, Ching-Yu Chin, Chun-Kai Wang, Hung-Ming Chen
2015 J jnl
A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen, Tung-Chieh Chen, Chin-Chieh Lee, Jou-Chun Lin
2015 — conf
Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability.
ISPD
Chun-Kai Wang, Chuan-Chia Huang, Shih-Ying Sean Liu, Ching-Yu Chin, Sheng-Te Hu, Wei-Chen Wu, Hung-Ming Chen
2014 J jnl
Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation.
ACM Trans. Design Autom. Electr. Syst.
Chun-Kai Wang, Yeh-Chi Chang, Hung-Ming Chen, Ching-Yu Chin
2014 J jnl
Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function.
IEEE Trans. Very Large Scale Integr. Syst.
Shih-Ying Sean Liu, Ren-Guo Luo, Suradeth Aroonsantidecha, Ching-Yu Chin, Hung-Ming Chen
2013 A conf
Efficient analog layout prototyping by layout reuse with routing preservation.
ICCAD
Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin
2013 J jnl
Escaped Boundary Pins Routing for High-Speed Boards.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ching-Yu Chin, Chung-Yi Kuan, Tsung-Ying Tsai, Hung-Ming Chen, Yoji Kajitani
2012 — conf
A fast thermal aware placement with accurate thermal analysis based on Green function.
ASP-DAC
Suradeth Aroonsantidecha, Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen
2011 J jnl
A Novel Test Flow for One-Time-Programming Applications of NROM Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Mango Chia-Tso Chao, Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang
2011 A conf
On routing fixed escaped boundary pins for high speed boards.
DATE
Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani
2010 A conf
Mathematical yield estimation for two-dimensional-redundancy memory arrays.
ICCAD
Mango Chia-Tso Chao, Ching-Yu Chin, Chen-Wei Lin
2009 A conf
A novel test flow for one-time-programming applications of NROM technology.
ITC
Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang, Mango Chia-Tso Chao
2009 A* conf
Fault models for embedded-DRAM macros.
DAC
Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin