Ching-Yi Huang

27 papers A 10B 1C 2Journal 8Unranked 6
YearRankTypeTitle / Venue / Authors
2020 A conf
ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk.
ICCAD
Chih-Jen Hsu, Chi-An Wu, Ching-Yi Huang, Kei-Yong Khoo
2019 A conf
2019 CAD Contest: Logic Regression on High Dimensional Boolean Space.
ICCAD
Ching-Yi Huang, Chi-An (Rocky) Wu, Tung-Yuan Lee, Chih-Jen (Jacky) Hsu, Kei-Yong Khoo
2018 — conf
Using range-equivalent circuits for facilitating bounded sequential equivalence checking.
VLSI-DAT
Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin, Chun-Yao Wang
2017 J jnl
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays.
IEEE Trans. Very Large Scale Integr. Syst.
Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan
2017 A conf
ICCAD-2017 CAD contest in resource-aware patch generation.
ICCAD
Ching-Yi Huang, Chih-Jen Hsu, Chi-An Wu, Kei-Yong Khoo
2016 J jnl
An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm.
J. Multiple Valued Log. Soft Comput.
Tai-Lin Chen, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen
2016 J jnl
Area-Aware Decomposition for Single-Electron Transistor Arrays.
ACM Trans. Design Autom. Electr. Syst.
Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suman Datta, Vijaykrishnan Narayanan
2016 J jnl
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays.
IEEE Trans. Very Large Scale Integr. Syst.
Ching-Yi Huang, Yun-Jui Li, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
2016 — conf
MajorSat: A SAT solver to majority logic.
ASP-DAC
Yu-Min Chou, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang
2016 J jnl
Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks.
IEEE Trans. Multi Scale Comput. Syst.
Chen-Yu Lin, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Chiou-Ting Hsu
2015 — conf
A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays.
ASP-DAC
Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
2015 J jnl
Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ching-Yi Huang, Zheng-Shan Yu, Yung-Chun Hu, Tung-Chen Tsou, Chun-Yao Wang, Yung-Chih Chen
2015 — conf
Synthesis and verification of cyclic combinational circuits.
SoCC
Jui-Hung Chen, Yung-Chih Chen, Wan-Chen Weng, Ching-Yi Huang, Chun-Yao Wang
2015 J jnl
Synthesis for Width Minimization in the Single-Electron Transistor Array.
IEEE Trans. Very Large Scale Integr. Syst.
Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan
2015 A conf
Using structural relations for checking combinationality of cyclic circuits.
DATE
Wan-Chen Weng, Yung-Chih Chen, Jui-Hung Chen, Ching-Yi Huang, Chun-Yao Wang
2014 A conf
Rewiring for threshold logic circuit minimization.
DATE
Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang
2014 A conf
Width minimization in the Single-Electron Transistor array synthesis.
DATE
Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
2013 A conf
On reconfigurable single-electron transistor arrays synthesis using reordering techniques.
DATE
Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
2013 C conf
Pattern generation for Mutation Analysis using Genetic Algorithms.
ISCAS
Yen-Chi Yang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen
2013 A conf
Sensitization criterion for threshold logic circuits and its application.
ICCAD
Chen-Kuan Tsai, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen
2013 J jnl
Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang
2012 A conf
A probabilistic analysis method for functional qualification under Mutation Analysis.
DATE
Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen
2012 — conf
Error Injection & Correction: An efficient formal logic restructuring algorithm.
ISOCC
Ching-Yi Huang, Daw-Ming Lee, Chun-Chi Lin, Chun-Yao Wang
2012 B conf
Using "Learning Video Portfolio" to Enhance Students' Metacognition in Authentic Learning.
ICALT
Ching-Yi Huang, Chi-Wen Huang, Chia-Jung Wu, Gwo-Dong Chen, Kuang-Hung Chiang
2012 C conf
Using Kinect to Track Learning Behavior of Students in the Classroom as Video Portfolio to Enhance Reflection Learning.
ICCE
Chuan-Ling Lien, Ching-Yi Huang, Chin-Yeh Wang, Gwo-Dong Chen
2011 — conf
A register-transfer level testability analyzer.
SoCC
Yen-An Chen, Chun-Yao Wang, Ching-Yi Huang, Hsiu-Yi Lin
2011 A conf
On rewiring and simplification for canonicity in threshold logic circuits.
ICCAD
Pin-Yi Kuo, Chun-Yao Wang, Ching-Yi Huang