Ching-Te Chuang

147 papers A* 1A 19C 19Misc 9Journal 55Unranked 44

Year	Rank	Type	Title / Venue / Authors
2019	—	`conf`	28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications. SoCC Huan-Jan Tseng, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
2018	—	`conf`	0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process. SoCC Yun-Sheng Chan, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
2018	—	`conf`	28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications. VLSI-DAT Yi-Chun Wu, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
2017	J	`jnl`	A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. Shang-Lin Wu, Kuang-Yu Li, Po-Tsang Huang, Wei Hwang, Ming-Hsien Tu, Sheng-Chi Lung, Wei-Sheng Peng, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang
2017	C	`conf`	An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. ISCAS Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen, Chi-Shi Chen, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
2017	C	`conf`	Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. ISCAS Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang
2017	J	`jnl`	Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes. IEEE Trans. Biomed. Circuits Syst. Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
2016	J	`jnl`	A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line. Microelectron. J. Shang-Lin Wu, Chien-Yu Lu, Ming-Hsien Tu, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang
2016	C	`conf`	A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. ISCAS Yi-Wei Chiu, Yu-Hao Hu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang
2016	C	`conf`	An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. ISCAS Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
2016	—	`conf`	Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application. SoCC Ming Chen, Po-Tsang Huang, Shang-Lin Wu, Wei Hwang, Ching-Te Chuang
2016	A	`conf`	Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells. ISLPED Chang-Hung Yu, Pin Su, Ching-Te Chuang
2016	—	`conf`	Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling. ICICDT Jian-Hao Wang, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2016	C	`conf`	Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs. ISCAS Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015	J	`jnl`	A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist. IEEE Trans. Very Large Scale Integr. Syst. Chien-Yu Lu, Ching-Te Chuang, Shyh-Jye Jou, Ming-Hsien Tu, Ya-Ping Wu, Chung-Ping Huang, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao
2015	—	`conf`	All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. VLSI-DAT Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang
2015	—	`conf`	Energy-efficient gas recognition system with event-driven power control. SoCC Chun-Ying Huang, Po-Tsang Huang, Chih-Chao Yang, Ching-Te Chuang, Wei Hwang
2015	—	`conf`	Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices. ICICDT Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015	C	`conf`	Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. ISCAS Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015	—	`conf`	Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. SoCC Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015	C	`conf`	Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells. ISCAS Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2015	—	`conf`	Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications. VLSI-DAT Chih-Chao Yang, Po-Tsang Huang, Chun-Ying Huang, Ching-Te Chuang, Wei Hwang
2014	—	`conf`	0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS. A-SSCC Po-Tsang Huang, Shu-Lin Lai, Ching-Te Chuang, Wei Hwang, Jason Huang, Angelo Hu, Paul Kan, Michael Jia, Kimi Lv, Bright Zhang
2014	—	`conf`	18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. ISSCC Po-Tsang Huang, Lei-Chun Chou, Teng-Chieh Huang, Shang-Lin Wu, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ming-Hsiang Cheng, Yueh-lung Lin, Ho-Ming Tong
2014	J	`jnl`	2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications. IEEE Trans. Biomed. Circuits Syst. Po-Tsang Huang, Shang-Lin Wu, Yu-Chieh Huang, Lei-Chun Chou, Teng-Chieh Huang, Tang-Hsuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Ho-Ming Tong
2014	J	`jnl`	40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Yuan-Hua Chu, Shyh-Jye Jou, Ching-Te Chuang
2014	J	`jnl`	A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. Nan-Chun Lien, Li-Wei Chu, Chien-Hen Chen, Hao-I Yang, Ming-Hsien Tu, Paul-Sen Kan, Yong-Jyun Hu, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
2014	—	`conf`	A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. SoCC Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao
2014	C	`conf`	Energy-efficient configurable discrete wavelet transform for neural sensing applications. ISCAS Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
2014	—	`conf`	Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. VLSI-DAT Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
2014	C	`conf`	Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells. ISCAS Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2014	J	`jnl`	Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2014	J	`jnl`	Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices. IEEE Trans. Circuits Syst. I Regul. Pap. Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2014	C	`conf`	Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling. ISCAS Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2014	J	`jnl`	Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors. IEEE Trans. Circuits Syst. II Express Briefs Dao-Ping Wang, Hon-Jarn Lin, Ching-Te Chuang, Wei Hwang
2014	—	`conf`	PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. SoCC Pei-Chen Wu, Yi-Ping Kuo, Chung-Shiang Wu, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang
2014	J	`jnl`	Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits. Microelectron. Reliab. Ming-Long Fan, Shao-Yu Yang, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2014	A	`conf`	Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell. ISLPED Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2013	A	`conf`	A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. ISLPED Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang
2013	—	`conf`	A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. SoCC Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan, Yong-Jyun Hu
2013	C	`conf`	A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. ISCAS Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih
2013	—	`conf`	A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance. SoCC Chien-Yu Lu, Ching-Te Chuang
2013	—	`conf`	Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications. BioCAS Teng-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
2013	—	`conf`	Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates. ISQED Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2013	—	`conf`	Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits. ICICDT Shao-Yu Yang, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2013	—	`conf`	Low temperature (<180 °C) bonding for 3D integration. 3DIC Yan-Pin Huang, Ruoh-Ning Tzeng, Yu-San Chien, Ming-Shaw Shy, Teu-Hua Lin, Kuo-Hua Chen, Ching-Te Chuang, Wei Hwang, Chi-Tsung Chiu, Ho-Ming Tong, Kuan-Neng Chen
2013	—	`conf`	Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation. SoCC Nan-Chun Lien, Ching-Te Chuang, Wen-Rong Wu
2013	C	`conf`	Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. ISCAS Ming-Hung Chang, Shang-Yuan Lin, Pei-Chen Wu, Olesya Zakoretska, Ching-Te Chuang, Kuan-Neng Chen, Chen-Chao Wang, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang
2013	J	`jnl`	Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection. IEEE Trans. Very Large Scale Integr. Syst. Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown
2013	—	`conf`	Through-silicon-via-based double-side integrated microsystem for neural sensing applications. ISSCC Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong
2012	J	`jnl`	A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. IEEE Trans. Circuits Syst. II Express Briefs Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
2012	A	`conf`	A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. ISLPED Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang
2012	—	`conf`	A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. SoCC Yung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2012	J	`jnl`	A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing. IEEE J. Solid State Circuits Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Chien-Yu Lu, Yuh-Jiun Lin, Meng-Hsueh Wang, Huan-Shun Huang, Kuen-Di Lee, Wei-Chiang Shih, Shyh-Jye Jou, Ching-Te Chuang
2012	—	`conf`	A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance. ESSDERC Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Ming-Fu Tsai, Chia-Hao Pao, Pin Su, Ching-Te Chuang
2012	—	`conf`	A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits. APCCAS Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012	—	`conf`	An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. VLSI-DAT Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih
2012	C	`conf`	An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. ISCAS Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
2012	—	`conf`	Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. APCCAS Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
2012	—	`conf`	Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. VLSI-DAT Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang
2012	C	`conf`	High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. ISCAS Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2012	—	`conf`	Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source. ICICDT Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012	J	`jnl`	Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs. IEEE Trans. Very Large Scale Integr. Syst. Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012	—	`conf`	On-chip self-calibrated process-temperature sensor for TSV 3D integration. SoCC Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang
2012	—	`conf`	Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells. ESSDERC Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2012	A	`conf`	Testing strategies for a 9T sub-threshold SRAM. ITC Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang
2012	J	`jnl`	Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications. IEEE Trans. Circuits Syst. II Express Briefs Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2012	—	`conf`	Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM. APCCAS Ming-Fu Tsai, Jen-Huan Tsai, Ming-Long Fan, Pin Su, Ching-Te Chuang
2011	A	`conf`	8T single-ended sub-threshold SRAM with cross-point data-aware write operation. ISLPED Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang
2011	—	`conf`	A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. SoCC Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2011	J	`jnl`	Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity. IEEE J. Emerg. Sel. Topics Circuits Syst. Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2011	A	`conf`	Analysis of power-performance for ultra-thin-body GeOI logic circuits. ISLPED Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2011	J	`jnl`	Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices. IEEE Trans. Very Large Scale Integr. Syst. Hao-I Yang, Wei Hwang, Ching-Te Chuang
2011	J	`jnl`	Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Hao-I Yang, Shyh-Chyi Yang, Wei Hwang, Ching-Te Chuang
2011	J	`jnl`	Impacts of gate-oxide breakdown on power-gated SRAM. Microelectron. J. Hao-I Yang, Wei Hwang, Ching-Te Chuang
2011	J	`jnl`	SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang
2010	J	`jnl`	Self-Repairing SRAM Using On-Chip Detection and Compensation. IEEE Trans. Very Large Scale Integr. Syst. Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy
2010	J	`jnl`	Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang
2009	C	`conf`	A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry. ISCAS Amlan Ghosh, Richard B. Brown, Rahul M. Rao, Ching-Te Chuang
2009	—	`conf`	Asymmetrical Write-assist for single-ended SRAM operation. SoCC Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang
2009	A	`conf`	Design and analysis of ultra-thin-body SOI based subthreshold SRAM. ISLPED Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2009	J	`jnl`	Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics. IEEE J. Solid State Circuits Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Yue Tan
2009	C	`conf`	Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices. ISCAS Hao-I Yang, Ching-Te Chuang, Wei Hwang
2009	J	`jnl`	Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. Microelectron. Reliab. Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang
2009	C	`conf`	Modeling, Analysis, and TCAD of Nanoscale Devices and Circuits. ISCAS Ching-Te Chuang
2009	A	`conf`	Yield estimation of SRAM circuits using "Virtual SRAM Fab". ICCAD Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das
2008	J	`jnl`	An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process. IEEE J. Solid State Circuits Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, Kaushik Roy
2008	C	`conf`	Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. ISCAS Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang
2008	J	`jnl`	Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies. IEEE Trans. Very Large Scale Integr. Syst. Jente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, Fadi H. Gebara, Kevin J. Nowka
2008	Misc	`conf`	Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. VTS Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy
2008	Misc	`conf`	On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. VLSI Design Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown
2008	—	`conf`	On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. ISQED Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown
2008	Misc	`conf`	Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy
2008	C	`conf`	Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. ICCD Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang
2008	J	`jnl`	Reducing parasitic BJT effects in partially depleted SOI digital logic circuits. Microelectron. J. Koushik K. Das, Ching-Te Chuang, Richard B. Brown
2008	—	`conf`	Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. ISQED Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang
2007	Misc	`conf`	A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. VLSI Design Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang
2007	A	`conf`	A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. ISLPED Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang
2007	A	`conf`	Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. ISLPED Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang
2007	—	`conf`	Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI. ISQED Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong
2007	J	`jnl`	Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectron. J. Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
2007	—	`conf`	Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure. ISSCC Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, Kaushik Roy
2006	Misc	`conf`	High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header. VLSI Design Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang
2006	J	`jnl`	Modeling and Analysis of Leakage Currents in Double-Gate Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy
2005	Misc	`conf`	Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. VLSI Design Rajiv V. Joshi, S. S. Kang, N. Zamdmar, Anda Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez
2005	—	`conf`	Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
2005	A	`conf`	Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. ISLPED Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy
2004	Misc	`conf`	A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. VLSI Design Rajiv V. Joshi, K. Kroell, Ching-Te Chuang
2004	A	`conf`	Nanoscale CMOS circuit leakage power reduction by double-gate device. ISLPED Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang
2004	J	`jnl`	Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt trigger circuits. IEEE Trans. Circuits Syst. II Express Briefs Jente B. Kuang, Ching-Te Chuang
2004	—	`conf`	Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell. ESSCIRC Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Anirudh Devgan
2003	—	`conf`	Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. ISQED Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim
2003	A	`conf`	Design and CAD Challenges in sub-90nm CMOS Technologies. ICCAD Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri
2003	J	`jnl`	Influence and model of gate oxide breakdown on CMOS inverters. Microelectron. Reliab. Rosana Rodríguez, James H. Stathis, Barry P. Linder, Rajiv V. Joshi, Ching-Te Chuang
2003	—	`conf`	New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology. ESSCIRC Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown
2003	A	`conf`	New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. ISLPED Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown
2003	J	`jnl`	PD/SOI SRAM performance in presence of gate-to-body tunneling current. IEEE Trans. Very Large Scale Integr. Syst. Rajiv V. Joshi, Ching-Te Chuang, Samuel K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi
2003	A	`conf`	Strained-si devices and circuits for low-power applications. ISLPED Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang
2002	J	`jnl`	Analysis of the effect of the gate oxide breakdown on SRAM stability. Microelectron. Reliab. Rosana Rodríguez, James H. Stathis, Barry P. Linder, Steven P. Kowalczyk, Ching-Te Chuang, Rajiv V. Joshi, Gregory A. Northrop, Kerry Bernstein, Azeez J. Bhavnagarwala, Salvatore Lombardo
2001	J	`jnl`	Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology. IEEE J. Solid State Circuits Jente B. Kuang, David H. Allen, Ching-Te Chuang
2001	J	`jnl`	On the temperature dependence of hysteresis effect in floating-body partially depleted SOI CMOS circuits. IEEE J. Solid State Circuits Ruchir Puri, Ching-Te Chuang, Mark B. Ketchen, Mario M. Pelella, Michael G. Rosenfield
2001	—	`conf`	SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang
2000	A	`conf`	"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang
2000	Misc	`conf`	A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang
2000	J	`jnl`	Hysteresis effect in pass-transistor-based, partially depleted SOI CMOS circuits. IEEE J. Solid State Circuits Ruchir Puri, Ching-Te Chuang
2000	Misc	`conf`	SOI Digital Circuits: Design Issues. VLSI Design Ruchir Puri, Ching-Te Chuang
1999	A	`conf`	Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits. ISLPED Ruchir Puri, Ching-Te Chuang
1999	A*	`conf`	SOI Digital CMOS VLSI - a Design Perspective. DAC Ching-Te Chuang, Ruchir Puri
1998	J	`jnl`	SOI for digital CMOS VLSI: design considerations and advances. Proc. IEEE Ching-Te Chuang, Pong-Fei Lu, Carl J. Anderson
1997	J	`jnl`	A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. IEEE J. Solid State Circuits Charles F. Webb, Carl J. Anderson, Leon J. Sigal, Kenneth L. Shepard, John S. Liptay, James D. Warnock, Brian W. Curran, Barry Krumm, Mark D. Mayo, Peter J. Camporese, Eric M. Schwarz, Mark S. Farrell, Phillip J. Restle, Robert M. Averill III, Timothy J. Slegel, William V. Huott, Yuen H. Chan, Bruce Wile, Thao N. Nguyen, Philip G. Emma, Daniel K. Beece, Ching-Te Chuang, Cyril Price
1997	J	`jnl`	Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor. IBM J. Res. Dev. Leon J. Sigal, James D. Warnock, Brian W. Curran, Yuen H. Chan, Peter J. Camporese, Mark D. Mayo, William V. Huott, Daniel R. Knebel, Ching-Te Chuang, James P. Eckhardt, Philip T. Wu
1997	J	`jnl`	Floating-body effects in partially depleted SOI CMOS circuits. IEEE J. Solid State Circuits Pong-Fei Lu, Ching-Te Chuang, Jin Ji, Lawrence F. Wagner, Chang-Ming Hsieh, Jente B. Kuang, Louis Lu-Chen Hsu, Mario M. Pelella Jr., Shao-Fu Sanford Chu, Carl J. Anderson
1996	A	`conf`	Floating body effects in partially-depleted SOI CMOS circuits. ISLPED Pong-Fei Lu, Jin Ji, Ching-Te Chuang, Lawrence F. Wagner, Chang-Ming Hsieh, Jente Benedict Kuang, L. Hsu, Mario M. Pelella Jr., Shao-Fu Sanford Chu, Carl J. Anderson
1995	J	`jnl`	High-speed low-power cross-coupled active-pull-down ECL circuit. IEEE J. Solid State Circuits Ching-Te Chuang, B. Wu, C. J. Anderson
1994	J	`jnl`	High-speed low-power direct-coupled complementary push-pull ECL circuit. IEEE J. Solid State Circuits Ching-Te Chuang, Kenneth Chin
1993	J	`jnl`	High-speed low-power Darlington ECL circuit. IEEE J. Solid State Circuits Ching-Te Chuang, Kenneth Chin, Pong-Fei Lu, Hyun J. Shin
1993	J	`jnl`	Non-quasi-static effects in advanced high-speed bipolar circuits. IEEE J. Solid State Circuits B. S. Wu, Ching-Te Chuang, Kenneth Chin
1993	J	`jnl`	Power partition and emitter size optimization for bipolar ECL circuit. IEEE J. Solid State Circuits Hsueh Y. Hsieh, Kenneth Chin, Ching-Te Chuang
1992	J	`jnl`	12.8-ps 1.0-mW charge-buffered active pull-down NTL circuit. IEEE J. Solid State Circuits Kenneth Chin, Ching-Te Chuang, James D. Warnock
1992	J	`jnl`	High-speed low-power AC-coupled complementary push-pull ECL circuit. IEEE J. Solid State Circuits Ching-Te Chuang, Denny D. Tang
1992	J	`jnl`	High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage. IEEE J. Solid State Circuits Ching-Te Chuang, Kenneth Chin, Hyun J. Shin, Pong-Fei Lu
1992	J	`jnl`	On the leverage of high-f IEEE J. Solid State Circuits Ching-Te Chuang, Kenneth Chin, Johannes M. C. Stork, Gary L. Patton, Emmanuel F. Crabbé, James H. Comfort
1991	J	`jnl`	A high-speed low-power JFET pull-down ECL circuit. IEEE J. Solid State Circuits Hyun J. Shin, Pong-Fei Lu, Ching-Te Chuang
1991	J	`jnl`	High-speed low-power charge-buffered active-pull-down ECI circuit. IEEE J. Solid State Circuits Ching-Te Chuang, Kenneth Chin
1991	J	`jnl`	NTL with complementary emitter-follower driver: a high-speed low-power push-pull logic circuit. IEEE J. Solid State Circuits Ching-Te Chuang
1989	J	`jnl`	A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage. IEEE J. Solid State Circuits Kai-Yap Toh, Ching-Te Chuang, Tze-Chiang Chen, James D. Warnock
1988	J	`jnl`	A circuit concept for reducing soft error in high-speed memory cells. IEEE J. Solid State Circuits Denny D. Tang, Ching-Te Chuang