Ching-Te Chiu - RankMe

126 papers A 1B 11C 17Misc 21Journal 33Unranked 42

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	AiRDUNet: All-In-One Residual Dense U-Net with Automated Humidity Quality Assessment for Partial Wet Fingerprint Restoration and Recognition. AICAS Jui-Min Hsu, Ching-Te Chiu, Mao-Hsiu Hsu, Che-Wei Liao
2025	J	`jnl`	High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator. CoRR Kuan-Ting Lin, Ching-Te Chiu, Jheng-Yi Chang, Shi-Zong Huang, Yu-Ting Li
2025	—	`conf`	High Utilization Vision Transformer Accelerator with Flexible Dataflow. NewCAS Ting-Chun Lin, Ching-Te Chiu, Jhao-Wei Chen
2025	J	`jnl`	Inpainting Diffusion Synthetic and Data Augment With Feature Keypoints for Tiny Partial Fingerprints. IEEE Trans. Biom. Behav. Identity Sci. Mao-Hsiu Hsu, Yung-Ching Hsu, Ching-Te Chiu
2025	—	`conf`	Pedestrian Detection Based on Visible Guided Occlusion Handling. APSIPA Lien-Chieh Huang, Ching-Te Chiu, Yung-Cheng Su
2025	—	`conf`	Reconfigurable Dataflow and Tile Shape Optimization in SystemC-Based NoC of 1D PE Array Simulators integrated with TVM. AICAS Yu-Jen Chang, Ching-Te Chiu, Tzu-Chun Huang
2024	C	`conf`	Feature Points based Residual UNet with Nonlinear Decay Rate for Partial Wet Fingerprint Restoration and Recognition. ISCAS An-Ting Hsieh, Ching-Te Chiu, Tsai-Chieh Chen, Mao-Hsiu Hsu, Wenyong Long
2024	C	`conf`	Low DRAM Memory Access and Flexible Dataflow Convolutional Neural Network Accelerator based on RISC-V Custom Instruction. ISCAS Yi-Fan Chen, Yu-Jen Chang, Ching-Te Chiu, Ming-Long Huang, Geng-Ming Liang, Chao-Lin Lee, Jenq-Kuen Lee, Ping-Yu Hsieh, Wei-Chih Lai
2024	—	`conf`	MLDN-Net: Multi-Level Denoising Neural Network for Wet Fingerprint via Cyclic Multi-Variate Function. TAAI (1) Chao-Lin Kuo, Ching-Te Chiu, Mao-Hsiu Hsu
2024	Misc	`conf`	Multi-Layer Relation Knowledge Distillation For Fingerprint Restoration. ICASSP Yu-Min Chiu, Ching-Te Chiu, Dao-Heng Luo
2023	—	`conf`	CPGAN: Collective Punishment Generative Adversarial Network for Dry Fingerprint Image Enhancement. AICAS Yu-Chi Su, Ching-Te Chiu, Chih-Han Cheng, Kuan-Hsien Liu, Tsung-Chan Lee, Jia-Lin Chen, Jie-Yu Luo, Wei-Chang Chung, Yao-Ren Chang, Kuan-Ying Ho
2023	J	`jnl`	EfficientNet-eLite: Extremely Lightweight and Efficient CNN Models for Edge Devices by Network Candidate Search. J. Signal Process. Syst. Ching-Chen Wang, Ching-Te Chiu, Jheng-Yi Chang
2023	—	`conf`	Landmark-Based Adversarial Network for RGB-D Pose Invariant Face Recognition. AICAS Wei-Jyun Chen, Ching-Te Chiu, Ting-Chun Lin
2023	—	`conf`	Low Temperature and Dry Fingerprint Restoration with Ridge Loss and Orientation. NEWCAS Hsueh-Kai Kuo, Ching-Te Chiu, Lien-Chieh Huang
2023	—	`conf`	Machine Learning Based Action Recognition with Modular CNN. APSIPA ASC Shi-Zong Huang, Ching-Te Chiu, Yu-Jen Chang
2023	J	`jnl`	Multiple Training Stage Image Enhancement Enrolled With CCRGAN Pseudo Templates for Large Area Dry Fingerprint Recognition. IEEE Access Chih-Han Cheng, Ching-Te Chiu, Chia-Yu Kuan, Yu-Chi Su, Kuan-Hsien Liu, Tsung-Chan Lee, Jia-Lin Chen, Jie-Yu Luo, Wei-Chang Chung, Yao-Ren Chang, Kuan-Ying Ho
2023	J	`jnl`	PGT-Net: Progressive Guided Multi-task Neural Network for Small-area Wet Fingerprint Denoising and Recognition. CoRR Yu-Ting Li, Ching-Te Chiu, An-Ting Hsieh, Mao-Hsiu Hsu, Wenyong Long, Jui-Min Hsu
2023	—	`conf`	Pose Aware RGBD-based Face Recognition System With Hierarchical Bilinear Pooling. NEWCAS Shu-Yun Wu, Ching-Te Chiu, Yung-Ching Hsu
2023	Misc	`conf`	RGB-D Based Pose-Invariant Face Recognition Via Attention Decomposition Module. ICASSP Wei-Chen Lin, Ching-Te Chiu, Kuan-Chang Shih
2022	J	`jnl`	Chaos LiDAR Based RGB-D Face Classification System With Embedded CNN Accelerator on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. Ching-Te Chiu, Yu-Chun Ding, Wei-Chen Lin, Wei-Jyun Chen, Shu-Yun Wu, Chao-Tsung Huang, Chun-Yeh Lin, Chia-Yu Chang, Meng-Jui Lee, Shimazu Tatsunori, Tsung Chen, Fan-Yi Lin, Yuan-Hao Huang
2022	—	`conf`	Lightweight and Efficient Neural Network Using Progressively Greedy Search. AICAS Jheng-Yi Chang, Ching-Te Chiu, Pin-Hsuan Chen
2022	C	`conf`	Multi-View RGB-D Based 3D Point Cloud Face Model Reconstruction System. ISCAS Jie-Yu Luo, Ching-Te Chiu, An-Ting Hsieh
2022	C	`conf`	RGBD-based Hardware Friendly Head Pose Estimation System via Convolutional attention module. ISCAS Yen-Yu Cheng, Ching-Te Chiu, Yi-Fan Chen
2021	—	`conf`	3D Landmark-based Face Detection and Recognition System for Large Poses. APSIPA ASC Ching-Tung Tang, Ching-Te Chiu, Wei-Jyun Chen
2021	—	`conf`	Efficient 2D Keypoint-based Hand Pose Estimation. CSCI Shan-Chien Hsiao, Ching-Te Chiu
2021	C	`conf`	High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator. ISCAS Kuan-Ting Lin, Ching-Te Chiu, Jheng-Yi Chang, Shan-Chien Hsiao
2021	J	`jnl`	Object Detection in RGB-D Images via Anchor Box with Multi-Reduced Region Proposal Network and Multi-Pooling. J. Signal Process. Syst. Jiou-Ai Lin, Ching-Te Chiu, Yen-Yu Cheng
2021	J	`jnl`	Real-Time Block-Based Embedded CNN for Gesture Classification on an FPGA. IEEE Trans. Circuits Syst. I Regul. Pap. Ching-Chen Wang, Yu-Chun Ding, Ching-Te Chiu, Chao-Tsung Huang, Yen-Yu Cheng, Shih-Yi Sun, Chih-Han Cheng, Hsueh-Kai Kuo
2021	—	`conf`	Real-Time Edge Attention-Based Learning for Low-Light One-Stage Object Detection. APSIPA ASC Yen-Yu Pu, Ching-Te Chiu, Shu-Yun Wu
2020	—	`conf`	Deep Neural Network Compression with Knowledge Distillation Using Cross-Layer Matrix, KL Divergence and Offline Ensemble. APSIPA Hsing-Hung Chou, Ching-Te Chiu, Yi-Ping Liao
2020	Misc	`conf`	Depth Estimation From Single Image Through Multi-Path-Multi-Rate Diverse Feature Extractor. ICASSP Wen-Yi Lo, Ching-Te Chiu, Jie-Yu Luo
2020	J	`jnl`	ESSA: An energy-Aware bit-Serial streaming deep convolutional neural network accelerator. J. Syst. Archit. Lien-Chih Hsu, Ching-Te Chiu, Kuan-Ting Lin, Hsing-Huan Chou, Yen-Yu Pu
2020	J	`jnl`	EfficientNet-eLite: Extremely Lightweight and Efficient CNN Models for Edge Devices by Network Candidate Search. CoRR Ching-Chen Wang, Ching-Te Chiu, Jheng-Yi Chang
2020	Misc	`conf`	Fast Single-View 3D Object Reconstruction with Fine Details Through Dilated Downsample and Multi-Path Upsample Deep Neural Network. ICASSP Chia-Ho Hsu, Ching-Te Chiu, Chia-Yu Kuan
2020	Misc	`conf`	Fast and Accurate Embedded DCNN for Rgb-D Based Sign Language Recognition. ICASSP Ching-Chen Wang, Ching-Te Chiu, Chao-Tsung Huang, Yu-Chun Ding, Li-Wei Wang
2020	J	`jnl`	Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy. J. Signal Process. Syst. Yung-Chang Chang, Cihun-Siyong Alex Gong, Ching-Te Chiu
2020	J	`jnl`	Multi-teacher knowledge distillation for compressed video action recognition based on deep learning. J. Syst. Archit. Meng-Chieh Wu, Ching-Te Chiu
2020	Misc	`conf`	Object Detection with Color and Depth Images with Multi-Reduced Region Proposal Network and Multi-Pooling. ICASSP Jiou-Ai Lin, Ching-Te Chiu, Yen-Yu Cheng
2020	J	`jnl`	Real-Time Object Detection With Reduced Region Proposal Network via Multi-Feature Concatenation. IEEE Trans. Neural Networks Learn. Syst. Kuan-Hung Shih, Ching-Te Chiu, Jiou-Ai Lin, Yen-Yu Bu
2020	Misc	`conf`	Rgb-D Based Multi-Modal Deep Learning for Face Identification. ICASSP Tzu-Ying Lin, Ching-Te Chiu, Ching-Tung Tang
2020	—	`conf`	Semantic Segmentation via Enhancing Context Information by Fusing Multiple High-Level Features. SiPS Kuang-Chien Li, Ching-Te Chiu, Shan-Chien Hsiao
2019	B	`conf`	An Energy-Aware Bit-Serial Streaming Deep Convolutional Neural Network Accelerator. ICIP Lien-Chih Hsu, Ching-Te Chiu, Kuan-Ting Lin
2019	J	`jnl`	Filter-based deep-compression with global average pooling for convolutional networks. J. Syst. Archit. Ting-Yun Hsiao, Yung-Chang Chang, Hsin-Hung Chou, Ching-Te Chiu
2019	Misc	`conf`	Multi-teacher Knowledge Distillation for Compressed Video Action Recognition on Deep Neural Networks. ICASSP Meng-Chieh Wu, Ching-Te Chiu, Kun-Hsuan Wu
2019	Misc	`conf`	Real-time Object Detection via Pruning and a Concatenated Multi-feature Assisted Region Proposal Network. ICASSP Kuan-Hung Shih, Ching-Te Chiu, Yen-Yu Pu
2018	—	`conf`	Filter-based Deep-Compression with Global Average Pooling for Convolutional Networks. SiPS Ting-Yun Hsiao, Yung-Chang Chang, Ching-Te Chiu
2018	Misc	`conf`	PVDC: A Binary Descriptor Using Pore-Valley Disk Code Structure for High-Resolution Partial Fingerprint Recognition. ICASSP Pei-Yin Chou, Ching-Te Chiu
2018	Misc	`conf`	Resource Efficient Hardware Implementation for Real-Time Traffic Sign Recognition. ICASSP Huai-Mao Weng, Ching-Te Chiu
2018	J	`jnl`	Video Super-resolution using Edge-based Optical Flow and Intensity Prediction. J. Signal Process. Syst. Jen-Wen Wang, Ching-Te Chiu
2017	—	`conf`	Dry fingerprint detection for multiple image resolutions using ridge features. SiPS Chen-Jung Wu, Ching-Te Chiu
2017	Misc	`conf`	LBP edge-mapped descriptor using MGM interest points for face recognition. ICASSP Jou Lin, Ching-Te Chiu
2017	J	`jnl`	Low-complexity face recognition using contour-based binary descriptor. IET Image Process. Jou Lin, Ching-Te Chiu
2017	Misc	`conf`	Motion clustering with hybrid-sample-based foreground segmentation for moving cameras. ICASSP Yi-Chan Wu, Ching-Te Chiu
2017	Misc	`conf`	Patch-based HDR video processing for fast moving object reconstruction. ICNC Yu-Fu Mai, Ching-Te Chiu
2017	C	`conf`	Single image super-resolution using hybrid patch search and local self-similarity. ISCAS Shen-Li Lo, Ching-Te Chiu
2016	Misc	`conf`	A cost-effective minutiae disk code for fingerprint recognition and its implementation. ICASSP Tsai-Te Chu, Ching-Te Chiu
2016	C	`conf`	Binary descriptor based SIFT and hardware implementation. ISCAS Che-Yu Wu, Ching-Te Chiu, Yarsun Hsu
2016	Misc	`conf`	Fingerprint recognition with ridge features and minutiae on distortion. ICASSP Chu-Chiao Liao, Ching-Te Chiu
2015	—	`conf`	A real-time embedded system for human gait analysis. SiPS Yen Wen Chien, Ching-Te Chiu, I-Zan Wu
2015	C	`conf`	Accelerating AdaBoost algorithm using GPU for multi-object recognition. ISCAS Pin Yi Tsai, Yarsun Hsu, Ching-Te Chiu, Tsai-Te Chu
2015	J	`jnl`	Edge Curve Scaling and Smoothing with Cubic Spline Interpolation for Image Up-Scaling. J. Signal Process. Syst. Wei-Chen Wu, Tsun-Hsien Wang, Ching-Te Chiu
2015	J	`jnl`	Editorial: Signal Processing for Communication/Biomedical Systems and Reliability Improvement. J. Signal Process. Syst. Ching-Te Chiu, Lei Wang, Yin-Tsung Hwang
2015	Misc	`conf`	Local binary pattern orientation based face recognition. ICASSP Yi-Kang Shen, Ching-Te Chiu
2015	J	`jnl`	Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment. IEEE Trans. Multim. Tsun-Hsien Wang, Cheng-Wen Chiu, Wei-Chen Wu, Jen-Wen Wang, Chun-Yi Lin, Ching-Te Chiu, Jing-Jia Liou
2015	—	`conf`	Virtual HDR/LDR image synthesizer in multi-core platform. GlobalSIP Tsun-Hsien Wang, Jen-Wen Wang, Ching-Te Chiu
2014	J	`jnl`	A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector. IEEE Trans. Circuits Syst. I Regul. Pap. Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Jen-Ming Wu, Ching-Te Chiu, Shawn S. H. Hsu, Mau-Chung Frank Chang
2014	—	`conf`	Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements. VLSI-DAT Yung-Chang Chang, Li-Ren Huang, Hsing-Chuang Liu, Chih-Jen Yang, Ching-Te Chiu
2014	Misc	`conf`	Boosted multi-class object detection with parallel hardware implementation for real-time applications. ICASSP Yao-Tsung Yang, Ching-Te Chiu
2014	—	`conf`	Edge-based motion and intensity prediction for video super-resolution. GlobalSIP Jen-Wen Wang, Ching-Te Chiu
2014	—	`conf`	Gradient-based image up-scaling with local self similarity. GlobalSIP Loyon Kuo, Tsun-Hsien Wang, Ching-Te Chiu
2014	—	`conf`	Object recognition using bag of words with kernels for big data. ICCE-TW Che-Yu Wu, Ching-Te Chiu, Yarsun Hsu
2013	J	`jnl`	Data Center Switch for Load Balanced Fat-Trees. J. Signal Process. Syst. Wei-Chih Lai, Ching-Te Chiu
2013	Misc	`conf`	Depth-based posture recognition by radar and vision fusion for real-time applications. ICASSP I-Cheng Tsai, Ching-Te Chiu
2013	—	`conf`	Edge curve scaling and smoothing with cubic spline interpolation for image upscaling. SiPS Wei-Chen Wu, Tsun-Hsien Wang, Ching-Te Chiu
2013	B	`conf`	Edge curve scaling and smoothing with cubic spline interpolation. ICIP Wei-Chen Wu, Tsun-Hsien Wang, Ching-Te Chiu
2013	J	`jnl`	Embedded Transition Inversion Coding With Low Switching Activity for Serial Links. IEEE Trans. Very Large Scale Integr. Syst. Ching-Te Chiu, Wen-Chih Huang, Chih-Hsing Lin, Wei-Chih Lai, Ying-Fang Tsao
2013	—	`conf`	Human gait analysis by body segmentation and center of gravity. APSIPA Ying-Fang Tsao, Wen-Te Liu, Ching-Te Chiu
2013	J	`jnl`	Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. Ching-Te Chiu, Yu-Hao Hsu, Wei-Chih Lai, Jen-Ming Wu, Shawn S. H. Hsu, Yang-Syu Lin, Fanta Chen, Min-Sheng Kao, Yarsun Hsu
2013	—	`conf`	Low cost illumination invariant face recognition by down-up sampling self quotient image. APSIPA Li Lin, Ching-Te Chiu
2012	Misc	`conf`	A 5.8 Gbps uniform mapping data center switch. ICASSP Wei-Chih Lai, Ching-Te Chiu
2012	J	`jnl`	A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link. IEEE Trans. Circuits Syst. I Regul. Pap. Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu
2012	—	`conf`	A Study of NoC Topologies and Switching Arbitration Mechanisms. HPCC-ICESS Yung-Chang Chang, Ching-Te Chiu
2012	C	`conf`	A novel low gate-count serializer topology with Multiplexer-Flip-Flops. ISCAS Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu, Ying-Fang Tsao
2012	J	`jnl`	An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking. J. Signal Process. Syst. Ching-Te Chiu, Yu-Hao Hsu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Yarsun Hsu
2012	—	`conf`	Cluster-Based CAN with Enhanced Transmission Capability for Vehicle Networks. ICCVE Wei-Chiu Liu, Zhan-Yao Gu, Yarsun Hsu, Ching-Te Chiu
2011	J	`jnl`	A 0.64 mm IEEE Trans. Very Large Scale Integr. Syst. Chih-Rung Chen, Wei-Su Wong, Ching-Te Chiu
2011	C	`conf`	A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit. ISCAS Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Chih-Hsing Lin, Jen-Ming Wu, Ching-Te Chiu, Shuo-Hung Hsu
2011	—	`conf`	A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. ASP-DAC Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Wei-Chih Lai, Yarsun Hsu
2011	J	`jnl`	BiTA/SWCE: Image Enhancement With Bilateral Tone Adjustment and Saliency Weighted Contrast Enhancement. IEEE Trans. Circuits Syst. Video Technol. Wei-Ming Ke, Chih-Rung Chen, Ching-Te Chiu
2011	B	`conf`	Curve-based and image-based JND contrast analysis for inverse tone mapping operators. ICIP Chih-Rung Chen, Ching-Te Chiu
2011	—	`conf`	Embedded transition inversion coding for low power serial link. SiPS Wen-Chih Huang, Chih-Hsing Lin, Ching-Te Chiu
2011	B	`conf`	Handover Delay Reduction and Buffer-Based Data Recovery Scheme for Inter Multicast Broadcast Service Zone. GLOBECOM Sih-Kai Li, Jen-Shun Yang, Ching-Te Chiu, Po-Ting Yeh, Jenq-Neng Hwang
2011	B	`conf`	Low visual difference virtual high dynamic range image synthesizer from a single legacy image. ICIP Tsun-Hsien Wang, Ching-Te Chiu
2011	—	`conf`	On the design and analysis of fault tolerant NoC architecture using spare routers. ASP-DAC Yung-Chang Chang, Ching-Te Chiu, Shih-Yin Lin, Chung-Kai Liu
2011	J	`jnl`	Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform. J. Signal Process. Syst. Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay, Cyuan-Jhe Wu
2011	—	`conf`	Saliency prediction using scene motion for JND based video compression. SiPS Ruei-Jiun Wang, Ching-Te Chiu
2011	B	`conf`	Texture classification based low order local binary pattern for face recognition. ICIP Ching-Te Chiu, Cyuan-Jhe Wu
2010	C	`conf`	A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. ISCAS Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Yarsun Hsu
2010	C	`conf`	A novel MUX-FF circuit for low power and high speed serial link interfaces. ISCAS Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu
2010	C	`conf`	A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification. ISCAS Chih-Hsing Lin, Yung-Chang Chang, Wen-Chih Huang, Wei-Chih Lai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Chun-Ming Huang, Chih-Chyau Yang, Shih-Lun Chen
2010	C	`conf`	Hardware-efficient image enhancement with bilateral tone adjustment. ISCAS Wei-Ming Ke, Ching-Te Chiu
2010	J	`jnl`	Switching Bilateral Filter With a Texture/Noise Detector for Universal Noise Removal. IEEE Trans. Image Process. Chih-Hsing Lin, Jia Shiuan Tsai, Ching-Te Chiu
2010	Misc	`conf`	Switching bilateral filter with a texture/noise detector for universal noise removal. ICASSP Chih-Hsing Lin, Jia Shiuan Tsai, Ching-Te Chiu
2009	J	`jnl`	A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-µm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. Min-Sheng Kao, Jen-Ming Wu, Chih-Hsing Lin, Fanta Chen, Ching-Te Chiu, Shawn S. H. Hsu
2009	B	`conf`	A 100MHz hardware-efficient boost cascaded face detection design. ICIP Wei-Su Wong, Chih-Rung Chen, Ching-Te Chiu
2009	B	`conf`	Hardware-efficient virtual high dynamic range image reproduction. ICIP Wei-Ming Ke, Tsun-Hsien Wang, Ching-Te Chiu
2008	—	`conf`	A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology. SiPS Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay
2008	—	`conf`	A 2.64GHz wide range low power DLL-based frequency multiplier with CML circuits using adaptive body bias. ICECS Chih-Hsing Lin, Ching-Te Chiu
2008	C	`conf`	A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology. ISCAS Yu-Hao Hsu, Ming-Hao Lu, Ping-Ling Yang, Fanta Chen, You-Hung Li, Min-Sheng Kao, Chih-Hsing Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu
2008	B	`conf`	Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video. ICIP Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Rong Chen, Rong Yang, Ren-Song Tsay
2007	C	`conf`	A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications. ISCAS Chih-Hsing Lin, Ching-Te Chiu
2007	—	`conf`	A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces. ASP-DAC Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu
2007	C	`conf`	A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. ISCAS Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu
2007	—	`conf`	Block-Based Gradient Domain High Dynamic Range Compression Design for Real-Time Applications. ICIP (3) Tsun-Hsien Wang, Wei-Ming Ke, Ding-Chuang Zwao, Fang-Chu Chen, Ching-Te Chiu
2007	—	`conf`	Design and Implementation of a Real-Time Global Tone Mapping Processor for High Dynamic Range Video. ICIP (6) Tsun-Hsien Wang, Wei-Su Wong, Fang-Chu Chen, Ching-Te Chiu
2007	—	`conf`	Design of ultra low power CML MUXs and latches with forward body bias. SoCC Hsiang-Ju Hsu, Ching-Te Chiu, Yarsun Hsu
2007	A	`conf`	Low Power Design of High Performance Memory Access Architecture for HDTV Decoder. ICME Tsun-Hsien Wang, Ching-Te Chiu
2006	B	`conf`	A Flexible Cross Connect LCAS for Bandwidth Maximization in 2.5G EoS. NCA Hou-Cheng Tzeng, Ching-Te Chiu
2005	—	`conf`	A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology. SoCC Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Chih-Hsien Jen, Yarsun Hsu
2005	—	`conf`	A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications. IWSOC Ching-Te Chiu, Chun-Chieh Chang, Shih-Min Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, Kai-Ming Feng
2005	B	`conf`	Design a simple and high performance switch using a two-stage architecture. GLOBECOM Chih-Ying Tu, Cheng-Shang Chang, Duan-Shin Lee, Ching-Te Chiu
1994	J	`jnl`	Optimal unified architectures for the real-time computation of time-recursive discrete sinusoidal transforms. IEEE Trans. Circuits Syst. Video Technol. K. J. Ray Liu, Ching-Te Chiu, Ravi K. Kolagotla, Joseph F. JáJá
1993	—	`conf`	Optimal unified IIR architectures for time-recursive discrete sinusoidal transforms. ICASSP (3) Kuo J. Ray Liu, Ching-Te Chiu, Ravi K. Kolagotla, Joseph F. JáJá
1993	J	`jnl`	Unified parallel lattice structures for time-recursive discrete cosine/sine/Hartley transforms. IEEE Trans. Signal Process. K. J. Ray Liu, Ching-Te Chiu
1992	J	`jnl`	Real-time parallel and fully pipelined two-dimensional DCT lattice structures with application to HDTV systems. IEEE Trans. Circuits Syst. Video Technol. Ching-Te Chiu, K. J. Ray Liu
1992	—	`—`	VLSI Algorithms and Architectures for Time-Recursive Discrete Sinuoidal Transforms with Applications to Real-Time Video Communications. Ching-Te Chiu