Ching-Hwa Cheng

62 papers A 2C 12Misc 4Journal 10Unranked 34

Year	Rank	Type	Title / Venue / Authors
2023	C	`conf`	A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy. ISCAS Jian-Lin Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng
2023	C	`conf`	Live Demonstration: A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy. ISCAS Jian-Lin Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng
2022	—	`conf`	A Low Power Two Lenses Wireless Panoramic Micro-Endoscopy Implemented Using Voltage-Current Adjuster and 3D-PCB Stacking Technology. BioCAS Xiang-Ren Yang, Sheng-Wei Hsu, Ching-Hwa Cheng, Don-Gey Liu
2022	—	`conf`	Live Demonstration: A Portable Four-Lenses Panoramic-Stereo Endoscope System Development. BioCAS Ching-Hwa Cheng, Don-Gey Liu
2021	J	`jnl`	A Multiple Layer U-Net, U IEEE Access Song-Toan Tran, Ching-Hwa Cheng, Don-Gey Liu
2021	C	`conf`	An Intelligent Image-Based Force Sensing System Development to Assist Robot-Arm Surgery. ISCAS Pham Minh Dung, Ching-Hwa Cheng, Don-Gey Liu
2021	—	`conf`	An Overlapping and Leading Edge Detection Combined Technique for Distance Estimation under High-Background Lights in a Pulsed-LiDAR System. IECC Thanh-Tuan Nguyen, Ching-Hwa Cheng, Don-Gey Liu, Song-Toan Tran, Minh-Hai Le
2021	C	`conf`	The Performance-Complexity Efficient Time-to-Digit and Data-Processing Chips Design and Validation for a LiDAR System. ISCAS Ching-Hwa Cheng, Ching-Kun Chao, Kai-Chun Yeh, Don-Gey Liu, Sheng-Di Lin
2020	—	`conf`	A Quantity Evaluation and Reconfiguration Mechanism for Signal- and Power-Interconnections in 3D-Stacking System. ASP-DAC Ching-Hwa Cheng
2020	—	`conf`	A Real-Time Robot-Arm Surgical Guiding System Development by Image-Tracking. AICAS Ching-Hwa Cheng
2020	C	`conf`	Design and Implementation of a Pre-Surgical Investigation System by VR+AR+MR Techniques. ISCAS Ching-Hwa Cheng, Huy Anh Nguyen, Tang-Chieh Liu
2020	C	`conf`	Development of a Portable Self-Guidance Rescue Car and a 3D-Screen LIDAR Mapping System. ISCAS Ching-Hwa Cheng, Pham Minh Dung, Tang-Chieh Liu
2020	—	`conf`	Low-Power 3D-PCB Stacking System Design and Validation by Automatic Voltage-Current Scalable Technique. VLSI-DAT Ching-Hwa Cheng, Jiun-In Guo
2019	—	`conf`	A Learnable Unmanned Smart Logistics Prototype System Design and Implementation. AICAS I-Lok Cheng, Ching-Hwa Cheng, Don-Gey Liu
2019	—	`conf`	A Stable Video Stitching Technique for Minimally Invasive Surgery. ICBET Dinh Thai Kim, Ching-Hwa Cheng, Don-Gey Liu
2019	C	`conf`	Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems. DDECS Ching-Hwa Cheng, Tang-Chieh Liu
2016	—	`conf`	A hierarchy multiple-voltage design technique for low-power performance-manageable bio-chips. ICCE-TW Yu-Shin Wang, Ching-Hwa Cheng
2016	—	`conf`	A variable-voltage low-power technique for digital circuit system. ASP-DAC An-Tai Xiao, Yung-Siang Miao, Ching-Hwa Cheng, Jiun-In Guo
2015	—	`conf`	A power-aware quad-voltage H.264 encoder chip for wireless panoramic endoscope applications. VLSI-DAT An-Tia Xiao, Shiang-Ren Yang, Yuan-Hsiang Miao, Ching-Hwa Cheng, Jiun-In Guo
2015	C	`conf`	A wireless panoramic endoscope system design and implementation for minimally invasive surgery. ISCAS Ching-Hwa Cheng, Sheng-Ping Hung, Jiun-In Guo, Kai-Che Liu, Jungle Chi-Hsiang Wu
2015	—	`conf`	An ECG front-end circuit with single power supply. ICCE-TW Hsiu-Cheng Lee, Jen-Bo Wang, Kai-Hsiang Juang, Kuo-Ching Hsiao, Hsung-Bie Chang, Yeng-Ting Lu, Ching-Sung Lee, Ming-Hsueh Hsiau, Qi-Ming Wan, Vu Duc Thai, Ching-Hwa Cheng, Don-Gey Liu
2015	J	`jnl`	SCKVdd: A Scalable Clock-Controlled Self-Stabilized Voltage Technique for Low Power CMOS Digital Circuits. ACM J. Emerg. Technol. Comput. Syst. Ching-Hwa Cheng
2014	C	`conf`	A panoramic endoscope design and implementation for Minimally Invasive Surgery. ISCAS Chun-Hsiang Peng, Ching-Hwa Cheng
2013	C	`conf`	A low-cost scalable Voltage-Frequency Adjustor for implementing low-power systems. ISCAS Ching-Hwa Cheng, Sheng-Wei Hsu, Jiun-In Guo
2013	J	`jnl`	Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor. VLSI Design Ching-Hwa Cheng
2013	—	`conf`	Integrated amorphous-Si TFT circuits for gate drivers on LCD panels. ASICON Nan-Xiong Huang, Hsi Rong Han, Wen Tui Liao, Chih-Hung Huang, Wen Chun Wang, Miin-Shyue Shiau, Ching-Hwa Cheng, Hong-Chong Wu, Heng-Shou Hsu, Juin J. Liou, Shry-Sann Liao, Ruei-Cheng Sun, Guang-Bao Lu, Don-Gey Liu
2013	J	`jnl`	Reduction of current mismatching in the switches-in-source CMOS charge pump. Microelectron. J. Miin-Shyue Shiau, Heng-Shou Hsu, Ching-Hwa Cheng, Hsiu-Hua Weng, Hong-Chong Wu, Don-Gey Liu
2012	—	`conf`	A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism. VLSI-DAT Ching-Hwa Cheng, Jiun-In Guo
2011	—	`conf`	A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. ASP-DAC Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng
2011	—	`conf`	A digitalized management mechanism for low-cost low-power multiple-voltage 3D designs. DSN Workshops Ching-Hwa Cheng, Ming-Hsuan Wu, Pin-Jui Lai, Chia-Hao Ku
2011	—	`conf`	A low-power management technique for high-performance domino circuits. ASP-DAC Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo
2011	—	`conf`	Built-in fine resolution clipping with calibration technique for high-speed testing by using wireless testers. DSN Workshops Ching-Hwa Cheng, Chen-I Chung
2011	—	`conf`	Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. ASP-DAC Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo
2010	—	`conf`	Built-in self at-speed delay binning and calibration mechanism in wireless test platform. ASP-DAC Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng
2010	—	`conf`	Dynamic voltage domain assignment technique for low power performance manageable cell based design. ASP-DAC Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo
2010	—	`conf`	Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. ASP-DAC Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, Ching-Hwa Cheng
2009	J	`jnl`	A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. ACM Trans. Design Autom. Electr. Syst. Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng
2009	C	`conf`	A Multi-standard Video Decoder for High Definition Video Applications. ISCAS Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng
2009	—	`conf`	A full-synthesizable high-precision built-in delay time measurement circuit. ASP-DAC Ming-Chien Tsai, Ching-Hwa Cheng
2009	J	`jnl`	CK IEICE Trans. Electron. Ching-Hwa Cheng, Chin-Hsien Wang
2009	—	`conf`	CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. ASP-DAC Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo
2009	—	`conf`	Design High-Performance and Low-Power Adder Cores with Full-Swing Nodes for Embedded Systems. IIH-MSP Ching-Hwa Cheng, Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung
2009	A	`conf`	Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. ITC Chen-I Chung, Shuo-Wen Chang, Ching-Hwa Cheng
2009	—	`conf`	Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test. Asian Test Symposium Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li
2008	Misc	`conf`	An All-Digital High-Precision Built-In Delay Time Measurement Circuit. VTS Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang
2007	—	`conf`	A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications. ISSCC Chih-Da Chien, Chien-Chang Lin, Yi-Hung Shih, He-Chun Chen, Chia-Jui Huang, Cheng-Yen Yu, Chih-Liang Chen, Ching-Hwa Cheng, Jiun-In Guo
2007	J	`jnl`	Fixed-outline floorplanning using robust evolutionary search. Eng. Appl. Artif. Intell. De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang, Ching-Hwa Cheng
2007	C	`conf`	Noise-Aware Floorplanning for Fast Power Supply Network Design. ISCAS Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang, Ching-Hwa Cheng
2007	Misc	`conf`	Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. VTS Hsiang-Hui Huang, Ching-Hwa Cheng
2003	—	`conf`	Design Scan Test Strategy for Single Phase Dynamic Circuits. DFT Ching-Hwa Cheng
2002	—	`conf`	Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits. DFT Ching-Hwa Cheng
2002	J	`jnl`	Novel Techniques for Improving Testability Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang
2001	J	`jnl`	Charge-sharing alleviation and detection for CMOS domino circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang
2000	—	`conf`	Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits. LATW Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
2000	—	`conf`	Charge sharing fault analysis and testing for CMOS domino logic circuits. Asian Test Symposium Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang
2000	—	`conf`	Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. DFT Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
2000	—	`conf`	Novel techniques for improving testability analysis. Asian Test Symposium Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang
2000	A	`conf`	Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. ICCAD Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang
1999	—	`conf`	Charge Sharing Fault Detection for CMOS Domino Logic Circuits. DFT Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone
1997	J	`jnl`	A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors. IEEE Trans. Computers Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng
1995	Misc	`conf`	An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. VLSI Design Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen
1994	Misc	`conf`	An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors. EDCC Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou