Ching-En Lee

13 papers A 1Misc 1Journal 8Unranked 3
YearRankTypeTitle / Venue / Authors
2022 J jnl
VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters.
IEEE J. Solid State Circuits
Junkang Zhu, Wei Tang, Ching-En Lee, Haolei Ye, Eric McCreath, Zhengya Zhang
2021 J jnl
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference.
IEEE J. Solid State Circuits
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang
2021 — conf
VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters.
VLSI Circuits
Junkang Zhu, Wei Tang, Ching-En Lee, Haolei Ye, Eric McCreath, Zhengya Zhang
2020 J jnl
A Pre-Bootstrapping Method for Use in Gate Driver Circuits to Improve the Scan Pulse Delay of High-Resolution TFT-LCD Systems.
IEEE Trans. Ind. Electron.
Chih-Lung Lin, Ming-Yang Deng, Wen-Ching Chiu, Li-Wei Shih, Jui-Hung Chang, Yu-Sheng Lin, Ching-En Lee
2019 J jnl
A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification.
IEEE J. Solid State Circuits
Thomas Chen, Ching-En Lee, Chester Liu, Zhengya Zhang
2019 — conf
SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS.
VLSI Circuits
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang
2019 A conf
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA.
FPGA
Cheng Fu, Shilin Zhu, Hao Su, Ching-En Lee, Jishen Zhao
2018 J jnl
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA.
CoRR
Cheng Fu, Shilin Zhu, Hao Su, Ching-En Lee, Jishen Zhao
2015 Misc conf
An error-compensated piecewise linear logarithmic arithmetic unit for phong lighting acceleration.
ACSSC
Ching-En Lee, Milos D. Ercegovac
2015 — conf
Reconfıgurable and selectively-adaptive signal processing for multi-mode wireless communication.
SiPS
Farhana Sheikh, Oskar Andersson, Ching-En Lee, Feng Xue, Chia-Hsiang Chen, Anuja Vaidya, Ankit Sharma, Tom Tetzlaff
2005 J jnl
A heuristic algorithm to minimize total weighted tardiness on a single machine with release times.
Int. Trans. Oper. Res.
Fuh-Der Chou, Tzu-Yun Chang, Ching-En Lee
2001 J jnl
A total standard WIP estimation method for wafer fabrication.
Eur. J. Oper. Res.
Yu-Hsin Lin, Ching-En Lee
2000 J jnl
A bottleneck-based due-date assignment methodology.
Int. J. Manuf. Technol. Manag.
Yu-Jen Chang, Ching-En Lee