Ching-Che Chung

60 papers A* 1B 1C 2Journal 35Unranked 21

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A Low-Power Hierarchical CNN Hardware Accelerator for Bearing Fault Diagnosis. IEEE Trans. Instrum. Meas. Yu-Pei Liang, Yao-Shun Hsu, Ching-Che Chung
2024	J	`jnl`	Implementation of Lightweight Convolutional Neural Networks with an Early Exit Mechanism Utilizing 40 nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles. Sensors Yu-Pei Liang, Chen-Ming Chang, Ching-Che Chung
2023	J	`jnl`	A Multiplier-Free Convolution Neural Network Hardware Accelerator for Real-Time Bearing Condition Detection of CNC Machinery. Sensors Yu-Pei Liang, Ming-You Hung, Ching-Che Chung
2023	J	`jnl`	CNN Hardware Accelerator for Real-Time Bearing Fault Diagnosis. Sensors Ching-Che Chung, Yu-Pei Liang, Hong-Jin Jiang
2023	—	`conf`	Lightweight CNN hardware accelerator using the ternary quantization method for fault diagnosis of CNC machinery. ICCE-Taiwan Ching-Che Chung, Yu-Pei Liang, Jo-Chen Huang
2022	—	`conf`	A Body Channel Communication Transceiver with a 16x Oversampling CDR and Convolutional Codes. VLSI-DAT Ching-Che Chung, Yi-Ting Tsai
2022	J	`jnl`	A Maximum Logarithmic Maximum a Posteriori Probability Based Soft-Input Soft-Output Detector for the Coded Spatial Modulation Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Tsung-Hsien Liu, Ting-Xu Jiang, Ching-Che Chung, Yuan-Sun Chu
2020	—	`conf`	A DBN Hardware Accelerator for Auditory Scene Classification. ICCE-TW Ching-Che Chung, Huai-xiang Zhang, Ming-You Hung, Hong-Jin Jian
2020	J	`jnl`	Design of a human body channel communication transceiver using convolutional codes. Microelectron. J. Ching-Che Chung, Duo Sheng, Ming-Hsuan Li
2019	J	`jnl`	A fast phase tracking reference-less all-digital CDR circuit for human body channel communication. Microelectron. J. Ching-Che Chung, Duo Sheng, Ming-Chieh Li, Yi-Che Tsai
2019	—	`conf`	An All-Digital Temperature Sensor with Process and Voltage Variation Tolerance for IoT Applications. SoCC Ching-Che Chung, Hsin-Han Huang
2019	—	`conf`	Built-in Self-Test Circuits for All-digital Phase-Locked Loops. ICCE-TW Ching-Che Chung, Wei-Jung Chu, Yi-Ting Tsai
2019	—	`conf`	Design of a DBN Hardware Accelerator for Handwritten Digit Recognitions. ICCE-TW Ching-Che Chung, Yi-Zeng Lee, Huai-xiang Zhang
2017	J	`jnl`	A cell-based 5-MHz on-chip clock generator. Turkish J. Electr. Eng. Comput. Sci. Ching-Che Chung, Jhih-Wei Li
2017	—	`conf`	A reference-less all-digital transceiver for human body channel communication. VLSI-DAT Ching-Che Chung, Yi-Che Tsai, Ming-Chieh Li
2017	J	`jnl`	An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications. Microelectron. J. Ching-Che Chung, Chi-Yu Hou
2017	J	`jnl`	An area-efficient and wide-range digital DLL for per-pin deskew applications. Turkish J. Electr. Eng. Comput. Sci. Ching-Che Chung, Chien-Ying Yu
2016	J	`jnl`	A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling. IEEE Trans. Very Large Scale Integr. Syst. Ching-Che Chung, Wei-Siang Su, Chi-Kuang Lo
2016	J	`jnl`	A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology. IEICE Electron. Express Ching-Che Chung, Chi-Kuang Lo
2016	B	`conf`	An all-digital voltage sensor for static voltage drop measurements. SAS Ching-Che Chung, Mei-I Sun
2015	—	`conf`	A 1 Mb/s-40 Mb/s human body channel communication transceiver. VLSI-DAT Ching-Che Chung, Chi-Tung Chang, Chih-Yu Lin
2015	J	`jnl`	A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator. IEEE Trans. Very Large Scale Integr. Syst. Ching-Che Chung, Duo Sheng, Wei-Da Ho
2015	J	`jnl`	A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector. IEEE Trans. Very Large Scale Integr. Syst. Ching-Che Chung, Duo Sheng, Chang-Jun Li
2014	—	`conf`	All-digital delay-locked loop for 3D-IC die-to-die clock synchronization. VLSI-DAT Ching-Che Chung, Chi-Yu Hou
2014	—	`conf`	An all-digital on-chip abnormal temperature warning sensor for dynamic thermal management. SoCC Ching-Che Chung, Jhih-Wei Li
2014	—	`conf`	An all-digital phase-locked loop compiler with liberty timing files. VLSI-DAT Ching-Che Chung, Duo Sheng, Chen-Han Chen
2014	J	`jnl`	High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. Ching-Che Chung, Duo Sheng, Sung-En Shen
2014	J	`jnl`	High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications. IEICE Electron. Express Duo Sheng, Ching-Che Chung, Hsiu-Fan Lai, Shu-Syun Jhao
2014	J	`jnl`	Partial Parity Cache and Data Cache Management Method to Improve the Performance of an SSD-Based RAID. IEEE Trans. Very Large Scale Integr. Syst. Ching-Che Chung, Hao-Hsiang Hsu
2013	—	`conf`	A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices. VLSI-DAT Ching-Che Chung, Duo Sheng, Wei-Siang Su
2013	J	`jnl`	A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS. IEICE Electron. Express Ching-Che Chung, Duo Sheng, Wei-Da Ho
2013	—	`conf`	A high-resolution and one-cycle conversion time-to-digital converter architecture for PET image applications. EMBC Duo Sheng, Ching-Che Chung, Chih-Chung Huang, Jia-Wei Jian
2013	—	`conf`	A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance. VLSI-DAT Ching-Che Chung, Chang-Jun Li
2013	C	`conf`	An all-digital on-chip silicon oscillator with automatic VT range selection relative modeling. ISCAS Ching-Che Chung, Jhih-Wei Li
2012	J	`jnl`	A Low-Power DCO Using Interlaced Hysteresis Delay Cells. IEEE Trans. Circuits Syst. II Express Briefs Chien-Ying Yu, Ching-Che Chung, Chia-Jung Yu, Chen-Yi Lee
2012	J	`jnl`	A high-performance wear-leveling algorithm for flash memory system. IEICE Electron. Express Ching-Che Chung, Duo Sheng, Ning-Mi Hsueh
2012	—	`conf`	A low-complexity high-performance wear-leveling algorithm for flash memory system design. APCCAS Ching-Che Chung, Ning-Mi Hsueh
2012	—	`conf`	A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology. VLSI-DAT Ching-Che Chung, Duo Sheng, Wei-Da Ho
2012	J	`jnl`	An All-Digital Large-N Audio Frequency Synthesizer for HDMI Applications. IEEE Trans. Circuits Syst. II Express Briefs Ching-Che Chung, Duo Sheng, Chia-Lin Chang, Wei-Da Ho, Yang-Di Lin, Fang-Nien Lu
2011	J	`jnl`	A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology. IEICE Electron. Express Ching-Che Chung, Duo Sheng, Chia-Lin Chang
2011	J	`jnl`	A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications. J. Signal Process. Syst. Ching-Che Chung, Jui-Yuan Yu, Shiou-Ru Jang, Chen-Yi Lee
2011	J	`jnl`	A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology. IEEE J. Solid State Circuits Ching-Che Chung, Chiun-Yao Ko
2011	J	`jnl`	A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications. IEEE Trans. Very Large Scale Integr. Syst. Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2011	J	`jnl`	A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology. IEICE Electron. Express Ching-Che Chung, Duo Sheng, Sung-En Shen
2011	J	`jnl`	An Autocalibrated All-Digital Temperature Sensor for On-Chip Thermal Monitoring. IEEE Trans. Circuits Syst. II Express Briefs Ching-Che Chung, Cheng-Ruei Yang
2011	J	`jnl`	Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Ching-Che Chung, Chiun-Yao Ko, Sung-En Shen
2010	C	`conf`	An all-digital smart temperature sensor with auto-calibration in 65nm CMOS technology. ISCAS Ching-Che Chung, Cheng-Ruei Yang
2010	J	`jnl`	Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications. IEICE Electron. Express Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2008	J	`jnl`	A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems. IEEE Trans. Circuits Syst. II Express Briefs Jui-Yuan Yu, Ching-Che Chung, Chen-Yi Lee
2008	—	`conf`	An all digital spread spectrum clock generator with programmable spread ratio for SoC applications. APCCAS Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2007	—	`conf`	A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications. ISSCC Jui-Yuan Yu, Ching-Che Chung, Wan-Chun Liao, Chen-Yi Lee
2007	J	`jnl`	An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications. IEEE Trans. Circuits Syst. II Express Briefs Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2007	—	`conf`	An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems. SoCC Jui-Yuan Yu, Juinn-Ting Chen, Mei-Hui Yang, Ching-Che Chung, Chen-Yi Lee
2006	—	`conf`	A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications. APCCAS Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2006	J	`jnl`	A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications. IEEE J. Solid State Circuits Pao-Lung Chen, Ching-Che Chung, Jyh-Neng Yang, Chen-Yi Lee
2006	A*	`conf`	Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications. DAC Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang
2005	J	`jnl`	A portable digitally controlled oscillator using novel varactors. IEEE Trans. Circuits Syst. II Express Briefs Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee
2005	—	`conf`	An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications. ISCAS (5) Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee
2004	J	`jnl`	A new DLL-based approach for all-digital multiphase clock generation. IEEE J. Solid State Circuits Ching-Che Chung, Chen-Yi Lee
2003	J	`jnl`	An all-digital phase-locked loop for high-speed clock generation. IEEE J. Solid State Circuits Ching-Che Chung, Chen-Yi Lee