Chin Ngai Sze

16 papers A 3Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2014 J jnl
Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cheng-Kok Koh, Chin Ngai Sze
2012 A conf
Placement: Hot or Not?
ICCAD
Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan, Samuel I. Ward
2011 — conf
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.
ACM Great Lakes Symposium on VLSI
Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze
2011 — conf
Wire synthesizable global routing for timing closure.
ASP-DAC
Michael D. Moffitt, Chin Ngai Sze
2010 A conf
A methodology for propagating design tolerances to shape tolerances for use in manufacturing.
DATE
Shayak Banerjee, Kanak B. Agarwal, Chin Ngai Sze, Sani R. Nassif, Michael Orshansky
2008 A conf
Pyramids: an efficient computational geometry-based approach for timing-driven placement.
ICCAD
Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan
2008 J jnl
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
2008 — conf
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.
ISPD
David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
2007 — —
Algorithms for the scaling toward nanometer VLSI physical synthesis.
Chin Ngai Sze
2007 J jnl
Fast Algorithms for Slew-Constrained Minimum Cost Buffering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze
2007 J jnl
Path-Based Buffer Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
2005 J jnl
Navigating Register Placement for Low Power Clock Network Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2003 — conf
Performance-driven multi-level clustering for combinational circuits.
ASP-DAC
Chin Ngai Sze, Ting-Chi Wang
2002 J jnl
Accelerating Logic Rewiring Using Implication Analysis Tree.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chin Ngai Sze, Wangning Long, Yu-Liang Wu, Jinian Bian
2001 — conf
Improved alternative wiring scheme applying dominator relationship.
ASP-DAC
Chin Ngai Sze, Yu-Liang Wu
2000 — conf
On improved graph-based alternative wiring scheme for multi-level logic optimization.
ICECS
Yu-Liang Wu, Chin Ngai Sze, Chak-Chung Cheung, Hongbing Fan