Chin-Long Wey

128 papers A* 3A 6C 20Misc 1Journal 39Unranked 59
YearRankTypeTitle / Venue / Authors
2019 J jnl
Machine Learning Classification for Assessing the Degree of Stenosis and Blood Flow Volume at Arteriovenous Fistulas of Hemodialysis Patients Using a New Photoplethysmography Sensor Device.
Sensors
Pei-Yu Chiang, Paul C.-P. Chao, Tse-Yi Tu, Yung-Hua Kao, Chih-Yu Yang, Der-Cherng Tarng, Chin-Long Wey
2019 — conf
Quality Evaluation via PPG on the AVFs of Hemodialysis Patients Based on Both Blood Flow Volume and Degree of Stenosis.
IEEE SENSORS
Pei-Yu Chiang, Paul C.-P. Chao, Tse-Yi Tu, Yung-Hua Kao, Chih-Yu Yang, Der-Cherng Tarng, Chin-Long Wey, Duc Huy Nguyen
2018 J jnl
A Portable, Wireless Photoplethysomography Sensor for Assessing Health of Arteriovenous Fistula Using Class-Weighted Support Vector Machine.
Sensors
Paul C.-P. Chao, Pei-Yu Chiang, Yung-Hua Kao, Tse-Yi Tu, Chih-Yu Yang, Der-Cherng Tarng, Chin-Long Wey
2018 — conf
Design and Implementation of OLED Driving and OPD Readout Circuitry for an Optical Vibration Sensor.
IEEE SENSORS
Yi-Cheng Wu, Yung-Hua Kao, Paul C.-P. Chao, Chin-Long Wey, Thilo Sauter, Fitrah P. Eka, Rajeev Pandey
2017 — conf
10.5 A three-level single-inductor triple-output converter with an adjustable flying-capacitor technique for low output ripple and fast transient response.
ISSCC
Li-Cheng Chu, Wen-Hau Yang, Xiaoqing Zhang, Yan-Jiun Lai, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
2017 — conf
2.3 A single-inductor dual-output converter with linear-amplifier-driven cross regulation for prioritized energy-distribution control of envelope-tracking supply modulator.
ISSCC
Shang-Hsien Yang, Yen-Ting Lin, Yu-Sheng Ma, Hung-Wei Chen, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
2017 — conf
20.2 Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor.
ISSCC
Wen-Jie Tsou, Wen-Hau Yang, Jian-He Lin, Hsin Chen, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
2017 — conf
A low quiescent current and cross regulation single-inductor dual-output converter with stacking MOSFET driving technique.
ESSCIRC
Yu-Sheng Ma, Wen-Hau Yang, Yen-Ting Lin, Hsin Chen, Li-Chi Lin, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai, Jui-Lung Chen
2017 — conf
A new reflective PPG LED-PD sensor module for cuffless blood pressure measurement at wrist artery.
IEEE SENSORS
Yung-Hua Kao, Paul C.-P. Chao, Yueh Hung, Chin-Long Wey
2017 — conf
Live demonstration: A novel cuffless photoplethysmography sensor for continuous blood pressure measurement.
IEEE SENSORS
Yung-Hua Kao, Paul C.-P. Chao, Yueh Hung, Chin-Long Wey
2017 J jnl
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chien-Chih Huang, Jwu-E Chen, Chin-Long Wey
2017 — conf
Unsymmetrical parallel switched-capacitor (UP-SC) regulator with fast searching optimum ratio technique.
ESSCIRC
Yen-Ting Lin, Wen-Hau Yang, Yu-Sheng Ma, Yan-Jiun Lai, Hung-Wei Chen, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai
2016 — conf
12.7 A 96%-efficiency and 0.5%-current-cross-regulation single-inductor multiple floating-output LED driver with 24b color resolution.
ISSCC
Hsiang-An Yang, Wen-Hau Yang, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai, Shin-Chi Lai
2016 — conf
93% Efficiency and 0.99 power factor in pseudo-linear LED driver.
A-SSCC
Shao-Wei Chiu, Chun-Chieh Kuo, Kai-Cheng Chuang, Wen-Hau Yang, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Lsung-Yen Lsai, Jui-Lung Chen
2016 — conf
95% light-load efficiency single-inductor dual-output DC-DC buck converter with synthesized waveform control technique for USB type-C.
VLSI Circuits
Wen-Hau Yang, Chiun-He Lin, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai, Jui-Lung Chen
2016 — conf
A digital low-dropout-regulator with steady-state load current (SLC) estimator and dynamic gain scaling (DGS) control.
APCCAS
Jian-He Lin, Wen-Jie Tsou, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Lsung-Yen Lsai
2016 — conf
A new cuffless optical sensor for blood pressure measuring with self-adaptive signal processing.
IEEE SENSORS
Yung-Hua Kao, Paul C.-P. Chao, Tse-Yi Tu, Keng-Yueh Chiang, Chin-Long Wey
2016 — conf
Lossless inductor current control in envelope tracking supply modulator with self-allocation of energy for optimzation of efficiency and EVM.
A-SSCC
Shang-Hsien Yang, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai
2016 J jnl
Multiplication of a Constant (2k ± 1) and Its Fast Hardware Implementation.
J. Signal Process. Syst.
Ping-Chang Jui, Chin-Long Wey, Muh-Tian Shiue
2016 — conf
Ultra-low voltage ripple in DC-DC boost converter by the pumping capacitor and wire inductance technique.
A-SSCC
Chen-Fan Tang, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai
2015 — conf
12.6 90% Peak efficiency single-inductor-multiple-output DC-DC buck converter with output independent gate drive control.
ISSCC
Yi-Ping Su, Chiun-He Lin, Shen-Yu Peng, Ru-Yu Huang, Te-Fu Yang, Shin-Hao Chen, Ting-Jung Lo, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai
2015 — conf
120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs.
ESSCIRC
Hsiang-An Yang, Chao-Chang Chiu, Shin-Chi Lai, Jui-Lung Chen, Chih-Wei Chang, Che-Hao Meng, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai, Hsin-Yu Luo
2015 — conf
200nA low quiescent current deep-standby mode in 28nm DC-DC buck converter for active implantable medical devices.
A-SSCC
Li-Cheng Chu, Te-Fu Yang, Ru-Yu Huang, Yi-Ping Su, Chiun-He Lin, Chin-Long Wey, Ke-Horng Chen, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai
2015 J jnl
Efficient Algorithm and Fast Hardware Implementation for Multiply-by-(1+2
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chin-Long Wey, Ping-Chang Jui, Muh-Tian Shiue
2015 J jnl
Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs.
ACM Trans. Design Autom. Electr. Syst.
Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo
2015 — conf
Pseudo AC current synthesizer and DC offset-corrected technique in constant-on-time control buck converter for werable electronics.
A-SSCC
Jui-Che Su, Wei-Chung Chen, Wei-Tin Lin, Ying-Wei Chou, Meng-Wei Chien, Chin-Long Wey, Ke-Horng Chen, Ying-Hsi Lin, Chao-Cheng Lee, Shian-Ru Lin, Tsung-Yen Tsai
2015 — conf
Suppressing output overshoot voltage technique with 47.1mW/μs power-recycling rate and 93% peak efficiency DC-DC converter for multi-core processors.
ESSCIRC
Meng-Wei Chien, Wen-Hau Yang, Ying-Wei Chou, Hsin-Chieh Chen, Wei-Chung Chen, Ke-Horng Chen, Chin-Long Wey, Shin-Chi Lai, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai, Hsin-Yu Luo
2014 — conf
17.10 0.65V-input-voltage 0.6V-output-voltage 30ppm/°C low-dropout regulator with embedded voltage reference for low-power biomedical systems.
ISSCC
Wei-Chung Chen, Yi-Ping Su, Yu-Huei Lee, Chin-Long Wey, Ke-Horng Chen
2014 — conf
A 20MS/s buck/boost supply modulator for envelope tracking applications with direct digital interface.
A-SSCC
Shang-Hsien Yang, Chin-Long Wey, Ke-Horng Chen, Ying-Hsi Lin, Jing-Jia Chen, Tsung-Yen Tsai, Chao-Cheng Lee
2014 — conf
A Class-D amplifier powered by embedded single-inductor bipolar-output power module with low common noise and dynamic voltage boosting technique.
ESSCIRC
Shin-Hao Chen, Kuei-Liang Lin, Shao Siang Ng, Ke-Horng Chen, Chin-Long Wey, Sheng Kang, Kevin Cheng, Li-Ren Huang, Chao-Jen Huang, Hsin-Yu Luo
2014 J jnl
A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique.
IEEE J. Solid State Circuits
Wei-Chung Chen, Su-Yi Ping, Tzu-Chi Huang, Yu-Huei Lee, Ke-Horng Chen, Chin-Long Wey
2014 — conf
A direct AC-DC and DC-DC cross-source energy harvesting circuit with analog iterating-based MPPT technique with 72.5% conversion efficiency and 94.6% tracking efficiency.
VLSIC
Tzu-Chi Huang, Ming-Jhe Du, Kuei-Liang Lin, Shao Siang Ng, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Jui-Lung Chen, Hung-Wei Chen
2014 C conf
A dual-level dual-phase pulse-width modulation class-D amplifier with 0.001% THD, 112 dB SNR.
ISCAS
Shang-Hsien Yang, Yuan-Han Yang, Ke-Horng Chen, Chung-Chih Hung, Chin-Long Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Zhih Han Tai, Yi Hsuan Cheng, Chi Chung Tsai, Hsin-Yu Luo, Shih-Ming Wang, Long-Der Chen, Cheng-Chen Yang, Huang Tian Hui
2014 — conf
Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology.
CICC
Hsin-Chieh Chen, Wei-Chung Chen, Ying-Wei Chou, Meng-Wei Chien, Chin-Long Wey, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chao-Cheng Lee
2014 J jnl
Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chin-Long Wey, Ping-Chang Jui, Gang-Neng Sung
2014 J jnl
Fast Charging and High Efficiency Switching-Based Charger With Continuous Built-In Resistance Detection and Automatic Energy Deliver Control for Portable Electronics.
IEEE J. Solid State Circuits
Tzu-Chi Huang, Ruei-Hong Peng, Tsu-Wei Tsai, Ke-Horng Chen, Chin-Long Wey
2014 — conf
Single inductor quad output switching converter with priority-scheduled program for fast transient and unlimited-load range in 40nm CMOS technology.
ESSCIRC
Wei-Chung Chen, Tzu-Chi Huang, Tsu-Wei Tsai, Ruei-Hong Peng, Kuei-Liang Lin, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Li-Ren Huang, Chao-Jen Huang, Chung-Chih Hung, Chin-Long Wey, Hsin-Yu Luo
2014 — conf
±3% voltage variation and 95% efficiency 28nm constant on-time controlled step-down switching regulator directly supplying to Wi-Fi systems.
VLSIC
Wei-Chung Chen, Yung-Sheng Huang, Meng-Wei Chien, Ying-Wei Chou, Hsin-Chieh Chen, Yi-Ping Su, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee
2013 C conf
A single-inductor programmable-output (SIPO) DC-DC converter for low power applications.
IECON
Chin-Long Wey, Chung-Hsien Hsu, Gang-Neng Sung
2013 — conf
A unitized charging and discharging smart battery management system.
ICCVE
Chin-Long Wey, Ping-Chang Jui
2013 — conf
A voltage-mode boost DC-DC converter with a constant-duty-cycle pulse control.
LASCAS
Chin-Long Wey, Chung-Hsien Hsu, Tai-Wei Chang
2013 — conf
Enhancement of Controller Area Network (CAN) bus arbitration mechanism.
ICCVE
Chin-Long Wey, Chung-Hsien Hsu, Kun-Chun Chang, Ping-Chang Jui
2013 — conf
Low-cost parallel FFT processors with conflict-free ROM-based twiddle factor generator for DVB-T2 applications.
MWSCAS
Ping-Chang Jui, Chin-Long Wey, Muh-Tian Shiue
2013 J jnl
Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits.
ACM Trans. Design Autom. Electr. Syst.
Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo
2012 — conf
A Fast 64-bit hybrid adder design in 90nm CMOS process.
MWSCAS
Shao-Kai Chang, Chin-Long Wey
2012 — conf
A fast hysteretic buck converter with adaptive ripple controller.
MWSCAS
Chin-Long Wey, Ze-Yan Li, Kun-Chun Chang, Gang-Neng Sung, Dennis K. Wey
2012 — conf
Efficient algorithm and hardware implementation of 3N for arithmetic and for Radix-8 encodings.
MWSCAS
Ping-Chang Jui, Gang-Neng Sung, Chin-Long Wey
2012 — conf
Generic Reliability Analysis for Safety-Critical FlexRay Drive-By-Wire Systems.
ICCVE
Kuen-Long Leu, Jwu-E Chen, Chin-Long Wey, Yung-Yuan Chen
2012 — conf
Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs).
ISVLSI
Pei-Wen Luo, Tao Wang, Chin-Long Wey, Liang-Chia Cheng, Bih-Lan Sheu, Yiyu Shi
2011 J jnl
A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs
Chi-Sheng Lin, Ting-Hsu Chien, Chin-Long Wey
2011 J jnl
A Low-Cost Continuous-Flow Parallel Memory-Based FFT Processor for UWB Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chin-Long Wey, Shin-Yo Lin, Hsu-Sheng Wang, Hung-Lieh Chen, Chun-Ming Huang
2011 J jnl
Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey
2011 — conf
Design of ultra-wide-load, high-efficient DC-DC buck converters.
ICECS
Chin-Long Wey, Chan-I Chiu, Kun-Chun Chang, Chung-Hsien Hsu, Gang-Neng Sung
2011 J jnl
Programmable System-on-Chip for Silicon Prototyping.
IEEE Trans. Ind. Electron.
Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Shih-Lun Chen, Chi-Shi Chen, Jiann-Jenn Wang, Kuen-Jong Lee, Chin-Long Wey
2011 J jnl
Reconfigurable Homogenous Multi-Core FFT Processor Architectures for Hybrid SISO/MIMO OFDM Wireless Communications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chin-Long Wey, Shin-Yo Lin, Pei-Yun Tsai, Ming-Der Shieh
2011 — conf
Yield-award placement optimization for Switched-Capacitor analog integrated circuits.
SoCC
Chien-Chih Huang, Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey
2010 J jnl
A Transceiver Front End for Electronic Control Units in FlexRay-Based Automotive Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chua-Chin Wang, Gang-Neng Sung, Po-Cheng Chen, Chin-Long Wey
2010 C conf
An effective phase detector for phase-locked loops with wide capture range and fast acquisition time.
ISCAS
Chi-Sheng Lin, Ting-Hsu Chien, Chin-Long Wey
2010 C conf
High-speed and low-power programmable frequency divider.
ISCAS
Ting-Hsu Chien, Chi-Sheng Lin, Chin-Long Wey, Ying-Zong Juang, Chun-Ming Huang
2010 J jnl
Low-cost FFT processor for DVB-T2 applications.
IEEE Trans. Consumer Electron.
Shin-Yo Lin, Chin-Long Wey, Ming-Der Shieh
2010 J jnl
Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey
2009 J jnl
An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops.
IEEE J. Solid State Circuits
Chi-Sheng Lin, Ting-Hsu Chien, Chin-Long Wey, Chun-Ming Huang, Ying-Zong Juang
2009 — conf
An edge-missing compensator for fast-settling wide-locking-range PLLs.
ISSCC
Ting-Hsu Chien, Chi-Sheng Lin, Ying-Zong Juang, Chun-Ming Huang, Chin-Long Wey
2009 C conf
Implementation and Prototyping of a Complex Multi-project System-on-a-chip.
ISCAS
Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Wei-De Chien, Shih-Lun Chen, Chi-Shi Chen, Jiann-Jenn Wang, Chin-Long Wey
2009 — conf
Robustness investigation of the FlexRay system.
SIES
Kuen-Long Leu, Chin-Long Wey, Jwu-E Chen, Yung-Yuan Chen
2009 — conf
Yield evaluation of analog placement with arbitrary capacitor ratio.
ISQED
Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey
2008 — conf
A low-cost continuous flow parallel memory-based FFT processor for Ultra-Wideband (UWB) applications.
APCCAS
Chin-Long Wey, Shin-Yo Lin, Hsu-Sheng Wang, Chun-Ming Huang
2008 J jnl
Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chin-Long Wey, Ming-Der Shieh, Shin-Yo Lin
2008 — conf
Design of square generator with small look-up table.
APCCAS
Wei-Chang Tsai, Ming-Der Shieh, Wen-Ching Lin, Chin-Long Wey
2008 J jnl
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu
2008 C conf
PrSoC: Programmable System-on-chip (SoC) for silicon prototyping.
ISCAS
Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Chin-Long Wey
2007 J jnl
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories
CoRR
Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey
2007 — conf
Design of cost-efficient memory-based FFT processors using single-port memories.
SoCC
Yao-Xian Yang, Jin-Fu Li, Hsiang-Ning Liu, Chin-Long Wey
2007 — conf
Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications.
ISVLSI
Chin-Long Wey, Wei-Chien Tang, Shin-Yo Lin
2007 — conf
High-speed, Low Cost Parallel Memory-Based FFT Processors for OFDM Applications.
ICECS
Chin-Long Wey, Shin-Yo Lin, Wei-Chien Tang, Muh-Tien Shiue
2006 C conf
Compressed domain content-based retrieval of MP3 audio example using quantization tree indexing and melody-line tracking method.
ISCAS
Tsung-Han Tsai, Yung-Tsung Wang, Jui Hong Hung, Chin-Long Wey
2006 — conf
Design of Reliable CMOS Phase-Locked Loops.
ICECS
Chin-Long Wey, Chi-Shu Huang, Shaolei Quan
2005 — conf
A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing.
ISCAS (4)
Shaolei Quan, Qiang Qiang, Chin-Long Wey
2005 A conf
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories.
DATE
Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey
2005 — conf
Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress.
DFT
Shaolei Quan, Meng-Yao Liu, Chin-Long Wey
2005 — conf
Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test.
Asian Test Symposium
Shaolei Quan, Qiang Qiang, Chin-Long Wey
2005 — conf
Reliability enhancement of CMOS SRAMs.
MTDT
Chin-Long Wey, Meng-Yao Liu, Shaolei Quan
2004 — conf
A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors.
ACM Great Lakes Symposium on VLSI
Shaolei Quan, Chin-Long Wey
2004 — conf
Burn-In Stress Test of Analog CMOS ICs.
Asian Test Symposium
Chin-Long Wey, Meng-Yao Liu
2004 — conf
Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement.
ACM Great Lakes Symposium on VLSI
Chin-Long Wey, Mohammad Athar Khalil, Jim Liu, Gregory Wierzba
2001 A conf
Extreme-voltage stress vector generation of analog CMOS ICs for gate-oxide reliability enhancement.
ITC
Mohammad Athar Khalil, Chin-Long Wey
2001 Misc conf
High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement.
VTS
Mohammad Athar Khalil, Chin-Long Wey
2000 J jnl
A fully differential current copier for performance improvement.
Int. J. Circuit Theory Appl.
Ren-Yuan Huang, Jin-Sheng Wang, Chin-Long Wey
2000 — conf
Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way.
Asian Test Symposium
Chin-Long Wey, Adam Osseiran, José Luis Huertas, Yeon-Chen Nieu
1998 J jnl
ATPRG: an automatic test program generator using HDL-A for fault diagnosis of analog/mixed-signal integrated circuits.
IEEE Trans. Instrum. Meas.
Wei-Hsing Huang, Chin-Long Wey
1998 J jnl
Design of a High-Speed Square Generator.
IEEE Trans. Computers
Chin-Long Wey, Ming-Der Shieh
1998 J jnl
Diagnosability analysis of analogue circuits.
Int. J. Circuit Theory Appl.
Wei-Hsing Huang, Chin-Long Wey
1998 J jnl
Fault macromodel for switches in switched-current circuits.
Int. J. Circuit Theory Appl.
Cheng-Ping Wang, Chin-Long Wey
1998 — conf
High-speed CMOS switched-current D/A converters for low-power/low-voltage signal processing applications.
ICECS
Jin-Sheng Wang, Chin-Long Wey
1998 A conf
Mapping Multiplication Algorithms into a Family of LUT-based FPGAs (Abstract).
FPGA
Manuel Jiménez, Chin-Long Wey, Michael A. Shanblatt
1998 C conf
Test points selection process and diagnosability analysis of analog integrated circuits.
ICCD
Wei-Hsing Huang, Chin-Long Wey
1997 C conf
Development of Hierarchical Testability Design Methodologies for Analog/Mixed-Signal Integrated Circuits.
ICCD
Cheng-Ping Wang, Chin-Long Wey
1996 J jnl
Built-in self-test (BIST) design of high-speed carry-free dividers.
IEEE Trans. Very Large Scale Integr. Syst.
Chin-Long Wey
1996 — conf
Mixed-signal circuit testing-A review.
ICECS
Chin-Long Wey
1996 C conf
On Design of Efficient Square Generator.
ICCD
Chin-Long Wey
1996 — conf
Test Generation Of Analog Switched-Current Circuits.
Asian Test Symposium
Cheng-Ping Wang, Chin-Long Wey
1995 C conf
A self-timed redundant-binary number to binary number converter for digital arithmetic processors.
ICCD
Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang
1995 J jnl
Application of Bipartite Graphs for Achieving Race-Free State Assignment.
IEEE Trans. Computers
Jun-Woo Kang, Chin-Long Wey, P. David Fisher
1995 C conf
Built-In Self Test (BIST) Design of High-Speed Carry-Free Dividers.
ISCAS
Chin-Long Wey
1995 C conf
High-radix SRT division with speculation of quotient digits .
ICCD
Tzu-Hsi Pan, Hyon-Sok Kay, Youngsun Chun, Chin-Long Wey
1995 J jnl
Simple yet accurate current copiers for low-voltage current-mode signal-processing applications.
Int. J. Circuit Theory Appl.
Ren-Yuan Huang, Chin-Long Wey
1995 J jnl
Test generation and concurrent error detection in current-mode A/D converters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chin-Long Wey, Shoba Krishnan, Sondes Sahli
1994 C conf
Concurrent Error Detection in High Speed Carry-free Division Using Alternative Input Data.
ICCD
Chin-Long Wey
1993 C conf
ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits.
ICCD
Chin-Long Wey, Ming-Der Shieh, P. David Fisher
1993 J jnl
An accurate reference-generating circuit for successive approximation current mode A/D converters.
Int. J. Circuit Theory Appl.
Shoba Krishnan, Chin-Long Wey
1993 C conf
Race-free state assignments using bipartite graphs.
ISCAS
Jun-Woo Kang, Chin-Long Wey, P. David Fisher
1992 A conf
Test Generation and Concurrent Error Detection in Current-Mode A/D Converters.
ITC
Shoba Krishnan, Sondes Sahli, Chin-Long Wey
1991 C conf
Concurrent Error Detection in Array Dividers by Alternating Input Data.
ICCD
Chin-Long Wey
1991 J jnl
Design of fault-diagnosable and repairable folded PLAs for yield enhancement.
IEEE J. Solid State Circuits
Chin-Long Wey, Tsin-Yuan Chang, Jyhyeuan Ding
1990 J jnl
An efficient output phase assignment for PLA minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chin-Long Wey, Tsin-Yuan Chang
1990 A* conf
Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement.
DAC
Chin-Long Wey, Jyhyeung Ding, Tsin-Yuan Chang
1990 C conf
Design of repairable and fully testable folded PLAs.
ICCD
Chin-Long Wey, Jyhyeung Ding
1989 J jnl
Design of fault diagnosable and repairable PLA's.
IEEE J. Solid State Circuits
Tsin-Yuan Chang, Chin-Long Wey
1989 A conf
Fault Location in Repairable Programmable Logic Arrays.
ITC
Chin-Long Wey
1989 C conf
OPAM: an efficient output phase assignment for multilevel logic minimization.
ICCD
Chin-Long Wey, Sin-Min Chang, Jing-Yang Jou
1988 J jnl
On yield consideration for the design of redundant programmable logic arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chin-Long Wey
1988 A* conf
PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs.
DAC
Chin-Long Wey, Tsin-Yuan Chang
1988 C conf
Test generation of C-testable array dividers.
ICCD
Chin-Long Wey, Sin-Min Chang
1988 J jnl
The design of concurrent error diagnosable systolic arrays for band matrix multiplications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shek-Wayne Chan, Chin-Long Wey
1987 A* conf
On Yield Consideration for the Design of Redundant Programmable Logic Arrays.
DAC
Chin-Long Wey
1987 J jnl
On a Novel Self-Test Approach to Digital Testing.
Comput. J.
Chin-Long Wey, Fabrizio Lombardi
1987 J jnl
On the Repair of Redundant RAM's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chin-Long Wey, Fabrizio Lombardi
1985 A conf
On a Multiprocessor System with Dynamic Redundancy.
RTSS
Fabrizio Lombardi, Chin-Long Wey