Chihiro Yoshimura

23 papers Journal 9Unranked 14
YearRankTypeTitle / Venue / Authors
2025 J jnl
Quantum Computer Architecture for Quantum Error Correction With Distributing Process to Multiple Temperature Layers.
Concurr. Comput. Pract. Exp.
Ryuji Ukai, Chihiro Yoshimura, Hiroyuki Mizuno
2024 J jnl
Active Inference With Empathy Mechanism for Socially Behaved Artificial Agents in Diverse Situations.
Artif. Life
Tadayuki Matsumura, Kanako Esaki, Shao Yang, Chihiro Yoshimura, Hiroyuki Mizuno
2024 J jnl
Response Style Characterization for Repeated Measures Using the Visual Analogue Scale.
IEEE Access
Shunsuke Minusa, Tadayuki Matsumura, Kanako Esaki, Yang Shao, Chihiro Yoshimura, Hiroyuki Mizuno
2024 J jnl
Response Style Characterization for Repeated Measures Using the Visual Analogue Scale.
CoRR
Shunsuke Minusa, Tadayuki Matsumura, Kanako Esaki, Yang Shao, Chihiro Yoshimura, Hiroyuki Mizuno
2023 — conf
Dynamical Perception-Action Loop Formation with Developmental Embodiment for Hierarchical Active Inference.
IWAI
Kanako Esaki, Tadayuki Matsumura, Shunsuke Minusa, Yang Shao, Chihiro Yoshimura, Hiroyuki Mizuno
2023 — conf
Quantum Computer Architecture for Quantum Error Correction with Distributing Process to Multiple Temperature Layers.
candar
Ryuji Ukai, Chihiro Yoshimura, Hiroyuki Mizuno
2022 — conf
Extended-Self Recognition for Autonomous Agent Based on Controllability and Predictability.
SSCI
Kanako Esaki, Tadayuki Matsumura, Chihiro Yoshimura, Hiroyuki Mizuno
2021 — conf
4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems.
ISSCC
Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Masato Hayashi, Masafumi Tada, Hiroaki Saito, Mayumi Mashimo, Masanao Yamaoka
2021 — conf
A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems.
A-SSCC
Kasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura, Mayumi Mashimo, Masanao Yamaoka
2020 J jnl
A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems.
IEEE J. Solid State Circuits
Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka
2020 — conf
CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem.
ASP-DAC
Chihiro Yoshimura, Masato Hayashi, Takashi Takemoto, Masanao Yamaoka
2019 — conf
A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems.
ISSCC
Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka
2019 — conf
A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems.
VLSI Circuits
Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka
2019 — conf
CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems.
CICC
Masanao Yamaoka, Takuya Okuyama, Masato Hayashi, Chihiro Yoshimura, Takashi Takemoto
2017 J jnl
Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing.
Int. J. Netw. Comput.
Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Masanao Yamaoka
2016 J jnl
A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing.
IEEE J. Solid State Circuits
Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
2016 J jnl
Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution.
Int. J. Netw. Comput.
Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
2016 J jnl
Assessing bluegill (Lepomis macrochirus) habitat suitability using partial dependence function combined with classification approaches.
Ecol. Informatics
Risa Shiroyama, Chihiro Yoshimura
2016 — conf
Computing architecture to perform approximated simulated annealing for Ising models.
ICRC
Takuya Okuyama, Chihiro Yoshimura, Masato Hayashi, Masanao Yamaoka
2016 — conf
FPGA-based Annealing Processor for Ising Model.
CANDAR
Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Masanao Yamaoka
2015 — conf
24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing.
ISSCC
Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
2015 — conf
An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution.
CANDAR
Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
2013 — conf
Spatial computing architecture using randomness of memory cell stability under voltage control.
ECCTD
Chihiro Yoshimura, Masanao Yamaoka, Hidetaka Aoki, Hiroyuki Mizuno